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M38021E2-XXXSP

M38021E2-XXXSP DataSheet Renesas Technology Corp 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES

8-BIT SINGLE-CHIP MICROCOMPUTER FAMILY 38000 SERIES

Renesas Technology Corp

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M38021E8-XXXFS M38022M4DXXXFS M38022M4DXXXSS M38022M6-XXXFS
M38022M6DXXXFP M38022M6DXXXFS M38022M6DXXXSS M38022M2-XXXFS
M38022M2-XXXSS M38022M2DXXXFS M38022M2DXXXSS M38022M1-XXXFP
M38022M1-XXXFS M38022M1-XXXSS M38022M1DXXXFP M38022M1DXXXFS
M38022M1DXXXSS M38026E1-XXXFP M38026E1-XXXFS M38026E1-XXXSS
M38026E1DXXXFP M38026E1DXXXFS M38026E1DXXXSS M38026E2-XXXFS
M38026E2-XXXSS M38023M3-XXXFP M38023M3-XXXFS M38023M3-XXXSS
M38026E4-XXXFS M38023E1-XXXFP M38023E1-XXXFS M38023E1-XXXSS
M38026M4-XXXFP M38026M4-XXXFS M38026M4-XXXSS M38025M1-XXXFP
M38023M6-XXXFP M38023M6-XXXFS M38023M6-XXXSS M38023M4DXXXFP
M38023M4DXXXFS M38023M4DXXXSS M38020E6-XXXFP M38020E6-XXXFS
M38022M3-XXXFP M38022M3-XXXFS M38022M3-XXXSS M38022M3DXXXFP
M38022M3DXXXFS M38022M3DXXXSS M38022E1-XXXFP M38022E1-XXXFS
M38022E1-XXXSS M38022E1DXXXFP M38022E1DXXXFS M38022E1DXXXSS
M38022E2-XXXFP M38022E2-XXXFS M38022E2-XXXSS M38023M5-XXXFP
M38022M5-XXXFP M38022M5-XXXFS M38022M5-XXXSS M38022M5DXXXFP
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M38020M6-XXXFS M38020M6-XXXSP M38020M6-XXXSS M38027M2-XXXSP
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M38021E1-XXXFP M38021E1-XXXFS M38021E1-XXXSP M38021E1-XXXSS

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
3802
Group
User's Manual
keep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Preface
This user's manual describes Mitsubishi's CMOS 8bit microcomputers 3802 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 3802 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the "SERIES MELPS 740 <SOFTWARE> USER'S MANUAL." For details of development support tools, refer to the "DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS" data book.
BEFORE USING THIS USER'S MANUAL
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. Be sure to refer to this chapter.
1. Organization
q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, electric characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bits
b7 b6 b5 b4 b3 b2 b1 b0 0
Bit attributes
(Note 1)
Contents immediately after reset release
CPU mode register (CPUM) [Address : 3B16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name
b1 b0
Function
0 0 : Single-chip mode 01: 1 0 : Not available 11: 0 : 0 page 1 : 1 page
At reset
RW
Processor mode bits
0 0 0 0 0 1
T T
Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0." Fix this bit to "0." Main clock (XIN-XOUT) stop bit Internal system clock selection bit
0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected
! !
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1. Contents immediately after reset release 0******"0" at reset release 1******"1" at reset release Undefined******Undefined or reset release T ******Contents determined by option at reset release Note 2. Bit attributes******The attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R******Read ******Read enabled !******Read disabled W******Write ******Write enabled ! ******Write disabled
LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS
3802 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user's manual is provided with standard functions. The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the detailed functions of each group, refer to the related data book and user's manual.
List of groups having the same functions
Group Function Pin (Package type) 3800 group
64 pin * 64P4B * 64P6N-A * 64P6D-A
As of September 1995 3806 group
80 pin * 80P6N-A * 80P6S-A * 80P6D-A
3802 group
64 pin * 64P4B * 64P6N-A
3807 group
80 pin * 80P6N-A
Clock generating circuit
1 circuit
1 circuit
1 circuit
2 circuit
<8-bit>
Timer
<8-bit> Prescaler : 3 Timer : 4
<8-bit> Prescaler : 3 Timer : 4
<8-bit> Prescaler : 3 Timer : 4
Timer : 3 <16-bit> Timer X/Y : 2 Timer A/B : 2 UART or Clock synchronous ! 1 Clock synchronous ! 1 8-bit ! 13-channel
UART or Clock synchronous ! 1
UART or Clock synchronous ! 1 Clock synchronous ! 1
UART or Clock synchronous ! 1 Clock synchronous ! 1 8-bit ! 8-channel
Serial I/O
A-D converter D-A converter Mask ROM Memory type One Time PROM EPROM RAM
8K 16K 24K 32K (Note 1) (Note 1) 16K 8K (Note 1) 16K 32K 32K V 8K
8-bit ! 8-channel
8-bit ! 2-channel 16K
(Note 1)
8-bit ! 2-channel
8-bit ! 4-channel 16K 16K 16K 512 Real time port output Analog comparator Watchdog timer
(Note 1)
(Note 1)
24K
32K 12K 16K 24K 32K 48K
(Note 1) (Note 1) (Note 1) (Note 3) (Note 3) (Note 3)
32K
(Note 1)
24K
(Note 2)
48K
(Note 3)
32K 384
24K
48K
(Note 2)
384 384 512 640 384 384
640 1024 384 384 512 1024 1024
PWM output
Remarks
Notes 1: 2: 3: V.
Extended operating temperature version available High-speed version available Extended operating temperature version and High-speed version available ROM expansion
Table of contents
Table of contents
CHAPTER 1. HARDWARE
DESCRIPTION . 1-2 FEATURES .. 1-2 APPLICATIONS . 1-2 PIN CONFIGURATION . 1-2 FUNCTIONAL BLOCK . 1-4 PIN DESCRIPTION . 1-5 PART NUMBERING . 1-6 GROUP EXPANSION . 1-7 GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) . 1-8 FUNCTIONAL DESCRIPTION . 1-9 Central Processing Unit (CPU) . 1-9 Memory .. 1-13 I/O Ports .. 1-15 Interrupts .. 1-18 Timers .. 1-20 Serial I/O.. 1-22 Pulse Width Modulation (PWM) . 1-28 A-D Converter . 1-30 D-A Converter . 1-31 Reset Circuit . 1-32 Clock Generating Circuit . 1-34 Processor Modes . 1-35 NOTES ON PROGRAMMING . 1-37 Processor Status Register . 1-37 Interrupts .. 1-37 Decimal Calculations . 1-37 Timers .. 1-37 Multiplication and Division Instructions . 1-37 Ports .. 1-37 Serial I/O.. 1-37 A-D Converter . 1-37 D-A Converter . 1-37 Instruction Execution Time . 1-37 Memory Expansion Mode. 1-37 Memory Expansion Mode and Microprocessor Mode . 1-37 DATA REQUIRED FOR MASK ORDERS . 1-38
3802 GROUP USER'S MANUAL
i
Table of contents
ROM PROGRAMMING METHOD . 1-38 FUNCTIONAL DESCRIPTION SUPPLEMENT .1-39 Interrupt .. 1-39 Timing After Interrupt . 1-40 A-D Converter . 1-41
CHAPTER 2. APPLICATION
2.1 I/O port .. 2-2 2.1.1 Memory map of I/O port . 2-2 2.1.2 Related registers . 2-3 2.1.3 Handling of unused pins . 2-4 2.2 Timer .. 2-5 2.2.1 Memory map of timer . 2-5 2.2.2 Related registers . 2-6 2.2.3 Timer application examples . 2-11 2.3 Serial I/O . 2-23 2.3.1 Memory map of serial I/O . 2-23 2.3.2 Related registers . 2-24 2.3.3 Serial I/O connection examples . 2-30 2.3.4 Setting of serial I/O transfer data format . 2-32 2.3.5 Serial I/O application examples . 2-33 2.4 PWM .. 2-53 2.4.1 Memory map of PWM . 2-53 2.4.2 Related registers . 2-54 2.4.3 PWM output circuit application example . 2-56 2.5 A-D converter . 2-59 2.5.1 Memory map of A-D conversion .2-59 2.5.2 Related registers . 2-60 2.5.3 A-D conversion application example .2-62 2.6 Processor mode . 2-64 2.6.1 Memory map of processor mode . 2-64 2.6.2 Related register . 2-64 2.6.3 Processor mode application examples . 2-65 2.7 Reset .. 2-69 2.7.1 Connection example of reset IC .2-69
CHAPTER 3. APPENDIX
3.1 Electrical characteristics . 3-2 3.1.1 Absolute maximum ratings . 3-2 3.1.2 Recommended operating conditions . 3-2 3.1.3 Electrical characteristics. 3-3
ii
3802 GROUP USER'S MANUAL
Table of contents
3.1.4 A-D converter characteristics . 3-3 3.1.5 D-A converter characteristics . 3-4 3.1.6 Timing requirements and Switching characteristics . 3-5 3.1.7 Absolute maximum ratings (Extended operating temperature version) . 3-9 3.1.8 Recommended operating conditions(Extended operating temperature version) . 3-9 3.1.9 Electrical characteristics (Extended operating temperature version) . 3-10 3.1.10 A-D converter characteristics (Extended operating temperature version) . 3-10 3.1.11 D-A converter characteristics (Extended operating temperature version) . 3-11 3.1.12 Timing requirements and Switching characteristics (Extended operating temperature version) . 3-12 3.1.13 Timing diagram . 3-14 3.2 Standard characteristics . 3-17 3.2.1 Power source current characteristic examples . 3-17 3.2.2 Port standard characteristic examples . 3-18 3.2.3 A-D conversion standard characteristics . 3-20 3.2.4 D-A conversion standard characteristics . 3-21 3.3 Notes on use. 3-22 3.3.1 Notes on interrupts . 3-22 3.3.2 Notes on the serial I/O1 . 3-22 3.3.3 Notes on the A-D converter . 3-23 3.3.4 Notes on the RESET pin . 3-24 3.3.5 Notes on input and output pins . 3-24 3.3.6 Notes on memory expansion mode and microprocessor mode . 3-25 3.3.7 Notes on built-in PROM . 3-26 3.4 Countermeasures against noise . 3-28 3.4.1 Shortest wiring length . 3-28 3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line . 3-29 3.4.3 Wiring to analog input pins . 3-30 3.4.4 Consideration for oscillator . 3-30 3.4.5 Setup for I/O ports . 3-31 3.4.6 Providing of watchdog timer function by software . 3-31 3.5 List of registers . 3-33 3.6 Mask ROM ordering method . 3-47 3.7 Mark specification form . 3-61 3.8 Package outline . 3-63 3.9 List of instruction codes . 3-65 3.10 Machine Instructions . 3-66 3.11 SFR memory map . 3-76 3.12 Pin configuration . 3-77
3802 GROUP USER'S MANUAL
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration of M38022M4-XXXFP .1-2 2 Pin configuration of M38022M4-XXXSP .1-3 3 Functional block diagram . 1-4 4 Part numbering . 1-6 5 Memory expansion plan . 1-7 6 Memory expansion plan (Extended operating temperature version) . 1-8 7 740 Family CPU register structure . 1-9 8 Register push and pop at interrupt generation and subroutine call . 1-10 9 Structure of CPU mode register . 1-11 10 Memory map diagram . 1-12 11 Memory map of special function register (SFR) . 1-13 12 Port block diagram (single-chip mode) (1) . 1-16 13 Port block diagram (single-chip mode) (2) . 1-17 14 Interrupt control . 1-18 15 Structure of interrupt-related registers . 1-18 16 Structure of timer XY register . 1-19 17 Block diagram of timer X, timer Y, timer 1, and timer 2 . 1-21 18 Block diagram of clock synchronous serial I/O1. 1-22 19 Operation of clock synchronous serial I/O1 function . 1-22 20 Block diagram of UART serial I/O . 1-23 21 Operation of UART serial I/O function . 1-24 22 Structure of serial I/O control registers . 1-25 23 Structure of serial I/O2 control register. 1-26 24 Block diagram of serial I/O2 function . 1-26 25 Timing of serial I/O2 function . 1-27 26 Timing of PWM cycle . 1-28 27 Block diagram of PWM function . 1-28 28 Structure of PWM control register. 1-29 29 PWM output timing when PWM register or PWM prescaler is changed . 1-29 30 Structure of AD/DA control register . 1-30 31 Block diagram of A-D converter . 1-30 32 Block diagram of D-A converter . 1-31 33 Equivalent connection circuit of D-A converter . 1-31 34 Example of reset circuit . 1-32 35 Internal status of microcomputer after reset . 1-32 36 Timing of reset . 1-33 37 Ceramic resonator circuit. 1-34 38 External clock input circuit . 1-34 39 Block diagram of clock generating circuit . 1-34 40 Memory maps in various processor modes . 1-35 41 Structure of CPU mode register . 1-35 42 ONW function timing . 1-36 43 Programming and testing of One Time PROM version . 1-38 44 Timing chart after an interrupt occurs . 1-40 45 Time up to execution of the interrupt processing routine . 1-40 46 A-D conversion equivalent circuit . 1-42 47 A-D conversion timing chart . 1-42
3802 GROUP USER'S MANUAL
i
List of figures CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port related registers . 2-2 Fig. 2.1.2 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6). 2-3 Fig. 2.1.3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6) . 2-3 Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.2.1 Memory map of timer related registers .2-5 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y . 2-6 2.2.3 Structure of Timer 1 . 2-6 2.2.4 Structure of Timer 2, Timer X, Timer Y .2-7 2.2.5 Structure of Timer XY mode register . 2-8 2.2.6 Structure of Interrupt request register 1 .2-9 2.2.7 Structure of Interrupt request register 2 .2-9 2.2.8 Structure of Interrupt control register 1 . 2-10 2.2.9 Structure of Interrupt control register 2 . 2-10 2.2.10 Connection of timers and setting of division ratios [Clock function] . 2-12 2.2.11 Setting of related registers [Clock function] . 2-13 2.2.12 Control procedure [Clock function] . 2-14 2.2.13 Example of a peripheral circuit .2-15 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] . 2-15 2.2.15 Setting of related registers [Piezoelectric buzzer output] . 2-16 2.2.16 Control procedure [Piezoelectric buzzer output] . 2-16 2.2.17 A method for judging if input pulse exists . 2-17 2.2.18 Setting of related registers [Measurement of frequency] . 2-18 2.2.19 Control procedure [Measurement of frequency] . 2-19 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width] . 2-20 2.2.21 Setting of related registers [Measurement of pulse width] . 2-21 2.2.22 Control procedure [Measurement of pulse width] . 2-22
2.3.1 Memory map of serial I/O related registers . 2-23 2.3.2 Structure of Transmit/Receive buffer register . 2-24 2.3.3 Structure of Serial I/O1 status register . 2-24 2.3.4 Structure of Serial I/O1 control register . 2-25 2.3.5 Structure of UART control register . 2-25 2.3.6 Structure of Baud rate generator .2-26 2.3.7 Structure of Serial I/O2 control register . 2-26 2.3.8 Structure of Serial I/O2 register. 2-27 2.3.9 Structure of Interrupt edge selection register . 2-27 2.3.10 Structure of Interrupt request register 1 . 2-28 2.3.11 Structure of Interrupt request register 2 . 2-28 2.3.12 Structure of Interrupt control register 1 . 2-29 2.3.13 Structure of Interrupt control register 2 . 2-29 2.3.14 Serial I/O connection examples (1) . 2-30 2.3.15 Serial I/O connection examples (2) . 2-31 2.3.16 Setting of Serial I/O transfer data format . 2-32 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O] . 2-33 2.3.18 Timing chart [Communication using a clock synchronous serial I/O] . 2-33 2.3.19 Setting of related registers at a transmitting side [Communication using a clock synchronous serial I/O] . 2-34 Fig. 2.3.20 Setting of related registers at a receiving side [Communication using a clock synchronous serial I/O] . 2-35
ii
3802 GROUP USER'S MANUAL
List of figures
Fig. 2.3.21 Control procedure at a transmitting side [Communication using a clock synchronous serial I/O] . 2-36 Fig. 2.3.22 Control procedure at a receiving side[Communication using a clock synchronous serial I/O] . 2-37 Fig. 2.3.23 Connection diagram [Output of serial data] . 2-38 Fig. 2.3.24 Timing chart [Output of serial data] . 2-38 Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data] . 2-39 Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data]. 2-39 Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data] . 2-40 Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data] . 2-41 Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data]. 2-41 Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data] . 2-42 Fig. 2.3.31 Connection diagram [Cyclic transmission or reception of block data between microcomputers] . 2-43 Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers] . 2-44 Fig. 2.3.33 Setting of related registers [Cyclic transmission or reception of block data between microcomputers] . 2-44 Fig. 2.3.34 Control in the master unit . 2-45 Fig. 2.3.35 Control in the slave unit . 2-46 Fig. 2.3.36 Connection diagram [Communication using UART] . 2-47 Fig. 2.3.37 Timing chart [Communication using UART] . 2-47 Fig. 2.3.38 Setting of related registers at a transmitting side [Communication using UART] . 2-49 Fig. 2.3.39 Setting of related registers at a receiving side [Communication using UART] . 2-50 Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART] . 2-51 Fig. 2.3.41 Control procedure at a receiving side [Communication using UART] . 2-52 Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.5.8 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 Memory map of PWM related registers . 2-53 Structure of PWM control register . 2-54 Structure of PWM prescaler . 2-54 Structure of PWM register . 2-55 Connection diagram . 2-56 PWM output timing . 2-56 Setting of related registers . 2-57 PWM output . 2-57 Control procedure . 2-58 Memory map of A-D conversion related registers . 2-59 Structure of AD/DA control register . 2-60 Structure of A-D conversion register . 2-60 Structure of Interrupt request register 2 . 2-61 Structure of Interrupt control register 2 . 2-61 Connection diagram [Conversion of Analog input voltage] . 2-62 Setting of related registers [Conversion of Analog input voltage] . 2-62 Control procedure [Conversion of Analog input voltage]. 2-63 Memory map of processor mode related register . 2-64 Structure of CPU mode register . 2-64 Expansion example of ROM and RAM . 2-65 Read-cycle (OE access, SRAM) . 2-66 Read-cycle (OE access, EPROM) . 2-66 Write-cycle (W control, SRAM). 2-67 Application example of the ONW function . 2-68
3802 GROUP USER'S MANUAL
iii
List of figures
Fig. 2.7.1 Example of Poweron reset circuit . 2-69 Fig. 2.7.2 RAM back-up system . 2-69
CHAPTER 3 APPENDIX
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 3.1.2 3.1.3 3.1.4 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 Circuit Timing Timing Timing for measuring output switching characteristics . 3-13 diagram (in single-chip mode) . 3-14 diagram (in memory expansion mode and microprocessor mode) (1) . 3-15 diagram (in memory expansion mode and microprocessor mode) (2) . 3-16
Power source current characteristic example . 3-17 Power source current characteristic example (in wait mode) . 3-17 Standard characteristic example of CMOS output port at P-channel drive(1) . 3-18 Standard characteristic example of CMOS output port at P-channel drive(2) . 3-18 Standard characteristic example of CMOS output port at N-channel drive(1) . 3-19 Standard characteristic example of CMOS output port at N-channel drive(2) . 3-19 A-D conversion standard characteristics . 3-20 D-A conversion standard characteristics . 3-21
Fig. 3.3.1 Structure of interrupt control register 2 . 3-22 Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 Wiring for the RESET pin . 3-28 Wiring for clock I/O pins . 3-29 Wiring for the VPP pin of the One Time PROM and the EPROM version . 3-29 Bypass capacitor across the VSS line and the VCC line . 3-29 Analog signal line and a resistor and a capacitor . 3-30 Wiring for a large current signal line . 3-30 Wiring to a signal line where potential levels change frequently . 3-30 Stepup for I/O ports . 3-31 Watchdog timer by software . 3-31
3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6). 3-33 3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6) . 3-33 3.5.3 Structure of Transmit/Receive buffer register . 3-34 3.5.4 Structure of Serial I/O1 status register . 3-34 3.5.5 Structure of Serial I/O1 control register . 3-35 3.5.6 Structure of UART control register . 3-35 3.5.7 Structure of Baud rate generator . 3-36 3.5.8 Structure of Serial I/O2 control register . 3-36 3.5.9 Structure of Serial I/O2 register . 3-37 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y . 3-37 3.5.11 Structure of Timer 1 . 3-38 3.5.12 Structure of Timer 2, Timer X, Timer Y . 3-38 3.5.13 Structure of Timer XY mode register . 3-39 3.5.14 Structure of PWM control register . 3-40 3.5.15 Structure of PWM prescaler .3-40 3.5.16 Structure of PWM register . 3-41 3.5.17 Structure of AD/DA control register . 3-42 3.5.18 Structure of A-D conversion register . 3-42 3.5.19 Structure of D-A 1 conversion, D-A 2 conversion register . 3-43 3.5.20 Structure of Interrupt edge selection register . 3-43 3.5.21 Structure of CPU mode register .3-44
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3802 GROUP USER'S MANUAL
List of figures
Fig. Fig. Fig. Fig. 3.5.22 3.5.23 3.5.24 3.5.25 Structure Structure Structure Structure of of of of Interrupt Interrupt Interrupt Interrupt request register 1 . request register 2 . control register 1 . control register 2 . 3-45 3-45 3-46 3-46
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List of tables
List of tables
CHAPTER 1 HARDWARE
Table Table Table Table Table Table Table Table Table Table Table 1 Pin description. 1-5 2 List of supported products . 1-7 3 List of supported products (Extended operating temperature version) . 1-8 4 Push and pop instructions of accumulator or processor status register . 1-10 5 Set and clear instructions of each bit of processor status register . 1-11 6 List of I/O port functions . 1-15 7 Interrupt vector addresses and priority . 1-18 8 Functions of ports in memory expansion mode and microprocessor mode . 1-35 9 Programming adapter . 1-38 10 Interrupt sources, vector addresses and interrupt priority. 1-39 11 Change of A-D conversion register during A-D conversion . 1-41
CHAPTER 2 APPLICATION
Table 2.1.1 Handling of unused pins (in single-chip mode) . 2-4 Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) . 2-4 Table 2.2.1 Function of CNTR0/CNTR1 edge switch bit . 2-8 Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values . 2-48
CHAPTER 3 APPENDIX
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 3.1.1 Absolute maximum ratings . 3-2 3.1.2 Recommended operating conditions .3-2 3.1.3 Electrical characteristics . 3-3 3.1.4 A-D converter characteristics. 3-3 3.1.5 D-A converter characteristics. 3-4 3.1.6 Timing requirements . 3-5 3.1.7 Timing requirements (2) . 3-5 3.1.8 Switching characteristics (1) .3-6 3.1.9 Switching characteristics (2) .3-6 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (1) . 3-7 3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (1) . 3-7 3.1.12 Timing requirements in memory expansion mode and microprocessor mode (2) . 3-8 3.1.13 Switching characteristics in memory expansion mode and microprocessor mode (2) . 3-8 3.1.14 Absolute maximum ratings (Extended operating temperature version) . 3-9 3.1.15 Recommended operating conditions (Extended operating temperature version) . 3-9 3.1.16 Electrical characteristics (Extended operating temperature version) . 3-10 3.1.17 A-D converter characteristics (Extended operating temperature version) . 3-10 3.1.18 D-A converter characteristics (Extended operating temperature version) . 3-11 3.1.19 Timing requirements (Extended operating temperature version) . 3-12 3.1.20 Switching characteristics (Extended operating temperature version) . 3-12
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i
List of tables
Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode (Extended operating temperature version) . 3-13 Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode (Extended operating temperature version) . 3-13 Table 3.3.1 Programming adapter . 3-26 Table 3.3.2 Setting of programming adapter switch . 3-26 Table 3.3.3 Setting of PROM programmer address . 3-27 Table 3.5.1 Function of CNTR0/CNTR1 edge switch bit . 3-39
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3802 GROUP USER'S MANUAL
CHAPTER 1 HARDWARE
DESCRIPTION FEATURES APPLICATIONS PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION
DESCRIPTION
The 3802 group is the 8-bit microcomputer based on the 740 family core technology. The 3802 group is designed for controlling systems that require analog signal processing and include two serial I/O functions, A-D converters, and D-A converters. The various microcomputers in the 3802 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3802 group, refer to the section on group expansion.
* Programmable input/output ports . 56 * Interrupts . 16 sources, 16 vectors * Timers . 8 bit ! 4 * Serial I/O1 . 8-bit ! 1 (UART or Clock-synchronized) * Serial I/O2 . 8-bit ! 1 (Clock-synchronized) * PWM . 8-bit ! 1 * A-D converter . 8-bit ! 8 channels * D-A converter . 8-bit ! 2 channels * Clock generating circuit . Internal feedback resistor * * * *
(connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage . 3.0 to 5.5 V (Extended operating temperature version : 4.0 to 5.5 V) Power dissipation . 32 mW Memory expansion possible Operating temperature range . -20 to 85C (Extended operating temperature version : -40 to 85C)
FEATURES
* Basic machine-language instructions . 71 * The minimum instruction execution time . 0.5 s
(at 8 MHz oscillation frequency)
* Memory size
ROM . 8 K to 32 K bytes RAM . 384 to 1024 bytes
APPLICATIONS
Office automation, VCRs, tuners, musical instruments, cameras, air conditioners, etc.
PIN CONFIGURATION (TOP VIEW)
P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15
41 40 38 37 39 36 35 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 15 14 16 1 3 4 5 7 2 6 8 9 47 43 42 34 33 45 44 46
P37/RD P36/WR P35/SYNC P34/ P33/RESETOUT P32/ONW P31/DA2 P30/DA1 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63 /AN3
32 31 30 29 28 27 26
M38022M4-XXXFP
25 24 23 22 21 20 19 18 17
P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 VSS XOUT XIN P40/INT4 P41/INT0 RESET CNVSS P42/INT1
Package type : 64P6N-A 64-pin plastic-molded QFP
Fig. 1 Pin configuration of M38022M4-XXXFP
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3802 GROUP USER'S MANUAL
P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT2
HARDWARE
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW)
VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT2 P42/INT1 CNVSS RESET P41/INT0 P40/INT4 XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P30/DA1 P31/DA2 P32/ONW P33/RESETOUT P34/ P35/SYNC P36/WR P37/RD P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7
Package type : 64P4B 64-pin shrink plastic-molded DIP
Fig.2 Pin configuration of M38022M4-XXXSP
3802 GROUP USER'S MANUAL
M38022M4-XXXSP
1-3
1-4
Reset input VSS VCC RESET
27 26 1 32
FUNCTIONAL BLOCK DIAGRAM (Package : 64P4B)
Clock input XIN CNVSS
Clock output XOUT
HARDWARE
Fig. 3 Functional block diagram
CPU
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
30
31
Clock generating circuit
RAM ROM
X Prescaler 12 (8) Y S PC H PS CNTR0 CNTR1 PCL Prescaler Y (8) Prescaler X (8)
A
Timer 1 (8) Timer 2 (8)
Timer X (8)
3802 GROUP USER'S MANUAL
PWM (8) SI/O2 (8) SI/O1 (8) D-A converter 2 (8) D-A converter 1 (8) INT0 ~ INT3 INT2 INT4
Timer Y (8)
A-D converter (8)
P6(8) P5(8)
P4(8)
P3(8)
P2(8)
P1(8)
P0(8)
2 12 13 14 15 16 17 18 19
3
4 5 6 7 8 9 10 11
20 21 22 23 24 25 28 29
57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
49 50 51 52 53 54 55 56
VREF AVSS
I/O port P6
I/O port P5
I/O port P4
I/O port P3
I/O port P2
I/O port P1
I/O port P0
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1. Pin description Pin VCC, VSS CNVSS Name Power source CNVSS Function Function except a port function * Apply voltage of 3.0 V-5.5 V to VCC, and 0 V to VSS. (Extended operating temperature version : 4.0 V to 5.5 V) * This pin controls the operation mode of the chip. * Normally connected to VSS. * If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed. * Reference voltage input pin for A-D and D-A converters * GND input pin for A-D and D-A converters * Connect to VSS. * Reset input pin for active "L" * Input and output signals for the clock generating circuit. * Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. * If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * The clock is used as the oscillating source of system clock. * * * * * * 8 bit CMOS I/O port I/O direction register allows each pin to be individually programmed as either input or output. At reset this port is set to input mode. In modes other than single-chip, these pins are used as address, data, and control bus I/O pins. CMOS compatible input level CMOS 3-state output structure * D-A conversion output pins
VREF AVSS RESET XIN XOUT
Analog reference voltage Analog power source Reset input Clock input Clock output
P00-P07 P10-P17 P20-P27 P30/DA1, P31/DA2 P32-P37 P40/INT4, P41/INT0, P42/INT1, P43/INT2 P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/SIN2, P51/SOUT2, P52/SCLK2, P53/SRDY2 P54/CNTR0, P55/CNTR1 P56/PWM P57/INT3 P60/AN0- P67/AN7
I/O port P0 I/O port P1 I/O port P2 I/O port P3
I/O port P4
* 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure
* External interrupt input pin
* Serial I/O1 I/O pins
I/O port P5
* 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure
* Serial I/O2 I/O pins
* Timer X and Timer Y I/O pins * PWM output pin * External interrupt input pin I/O port P6 * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure * A-D conversion input pins
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HARDWARE
PART NUMBERING
PART NUMBERING
Product
M3802 2 M 4 - XXX SP Package type SP : 64P4B package FP : 64P6N-A package SS : 64S1B-E package FS : 64D0 package ROM number Omitted in some types. Normally, using hyphen. When electrical characteristic, or division of quality identification code using alphanumeric character - : standard D : Extended operating temperature version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version
RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes
Fig.4 Part numbering
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HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 3802 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions ROM/PROM capacity . 8 K to 32 K bytes RAM capacity . 384 to 1024 bytes (2) Packages 64P4B . Shrink plastic molded DIP 64P6N-A . Plastic molded QFP 64S1B-E . Shrink ceramic DIP 64D0 . Ceramic LCC
Memory Expansion Plan
ROM size (bytes) 32K Mass product M38027M8/E8
28K Mass product 24K M38024M6
20K Mass product 16K M38022M4
12K Mass product 8K M38022M2
4K
192 256
384
512 RAM size (bytes)
640
768
896
1024
Fig. 5 Memory expansion plan
Currently supported products are listed below Table 2. List of supported products (P) ROM size (bytes) Product ROM size for User in ( ) M38022M2-XXXSP M38022M2-XXXFP M38022M4-XXXSP M38022M4-XXXFP M38024M6-XXXSP M38024M6-XXXFP M38027M8-XXXSP M38027E8-XXXSP M38027E8SP M38027M8-XXXFP M38027E8-XXXFP M38027E8FP M38027E8SS M38027E8FS 8192 (8062) 16384 (16254) 24576 (24446) As of May 1996 RAM size (bytes) 384 384 640 Package 64P4B 64P6N-A 64P4B 64P6N-A 64P4B 64P6N-A 64P4B 32768 (32638) Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version EPROM version
1024
64P6N-A 64S1B-E 64D0
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HARDWARE
GROUP EXPANSION
GROUP EXPANSION (Extended operating temperature version)
Mitsubishi plans to expand the 3802 group (extended operating temperature version) as follows: (1) Support for mask ROM One Time PROM, and EPROM versions ROM/PROM capacity . 8 K to 32 K bytes RAM capacity . 384 to 1024 bytes (2) Packages 64P4B . Shrink plastic molded DIP 64P6N-A . Plastic molded QFP
Memory Expansion Plan (Extended operating temperature version)
ROM size (bytes) 32K Mass product M38027M8D/E8D
28K
24K
20K Mass product 16K M38022M4D
12K Mass product 8K M38022M2D
4K
192 256
384
512 RAM size (bytes)
640
768
896
1024
Fig. 6 Memory expansion plan (Extended operating temperature version)
Currently supported products are listed below. Table 3. List of supported products (Extended operating temperature version) (P) ROM size (bytes) RAM size (bytes) Package Product M38022M2DXXXSP M38022M2DXXXFP M38022M4DXXXSP M38022M4DXXXFP M38027M8DXXXSP M38027E8DXXXSP M38027E8DSP M38027M8DXXXFP M38027E8DXXXFP M38027E8DFP 8192 (8062) 16384 (16254) 384 384 64P4B 64P6N-A 64P4B 64P6N-A 64P4B 32768 (32638) 1024 64P6N-A As of May 1996 Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank)
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3802 GROUP USER'S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 3802 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> Users Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instructions cannot be used. The MUL, DIV, WIT and STP instruction can be used. The central processing unit (CPU) has the six registers.
Stack pointer (S)
The stack pointer is an 8-bit register used during sub-routine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is "0", then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is "1", then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig.7.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to "1", the value contained in index register X becomes the address for the second OPERAND.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
b7
b0
A
b7 b0
Accumulator Index Register X
b0
X
b7
Y
b7 b0
Index Register Y Stack Pointer
b0
S
b15 b7
PCH
b7
PCL
b0
Program Counter
N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag
Fig. 7. 740 Family CPU register structure
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HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request (Note 1) Execute JSR M (S) Store Return Address on Stack (Note 2) (S) M (S) (S) (PCH) (S - 1) (PCL) (S - 1)
M (S) (S) M (S) (S) M (S) (S)
(PCH) (S - 1) (PCL) (S - 1) (PS) (S - 1) Store Contents of Processor Status Register on Stack Store Return Address on Stack (Note 2)
Subroutine Execute RTS Restore Return Address (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S)
Interrupt Service Routine
Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) (S + 1) M (S)
I Flag "0" to "1" Fetch the Jump Vector
Restore Contents of Processor Status Register
Restore Return Address
Note 1 : The condition to enable the interrupt
Interrupt enable bit is "1" Interrupt disable flag is "0" 2 : When an interrupt occurs, the address of the next instruction to be executed is stored in the stack area. When a subroutine is called, the address one before the next instruction to be executed is stored in the stack area.
Fig. 8. Register push and pop at interrupt generation and subroutine call
Table. 4. Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP
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3802 GROUP USER'S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to "1", but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". When an interrupt occurs, this flag is automatically set to "1" to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table. 5. Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag SEI CLI D flag SED CLD B flag _ _ T flag SET CLT V flag _ CLV N flag _ _
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HARDWARE
FUNCTIONAL DESCRIPTION
CPU Mode Register
The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Not used (return "0" when read)
Fig. 9. Structure of CPU mode register
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HARDWARE
FUNCTIONAL DESCRIPTION
Memory Special function register (SFR) area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Special page ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity (bytes) Address XXXX16
000016 SFR area 004016 010016 Zero page
192 256 384 512 640 768 896 1024
00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16
RAM
XXXX16 Reserved area 044016
ROM area
ROM capacity (bytes) Address YYYY16 Address ZZZZ16
Not used YYYY16 Reserved ROM area
(128 bytes)
4096 8192 12288 16384 20480 24576 28672 32768
F00016 E00016 D00016 C00016 B00016 A00016 900016 800016
F08016 E08016 D08016 C08016 B08016 A08016 908016 808016
ZZZZ16
ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page
Reserved ROM area
Fig. 10 Memory map diagram
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HARDWARE
FUNCTIONAL DESCRIPTION
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY)
PWM control register (PWMCON) PMW prescaler (PREPWM) PWM register (PWM)
AD/DA control register (ADCON) A-D conversion register (AD) D-A1 conversion register (DA1) D-A2 conversion register (DA2)
Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON)
003816 003916 003A16 003B16 003C16 003D16 003E16
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2)
Serial I/O2 register (SIO2)
003F16
Fig. 11 Memory map of special function register (SFR)
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FUNCTIONAL DESCRIPTION
I/O Ports Direction registers
The 3802 group has 56 programmable I/O pins arranged in seven I/O ports (ports P0 to P6). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
Table 6. list of I/O port functions Pin P00-P07 Name Port P0 Input/Output Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits I/O Format CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level Non-Port Function Address low-order byte output Address high-order byte output Related SFRs CPU mode register Ref.No.
P10-P17
Port P1
CPU mode register
(1)
P20-P27 P30/DA1 P31/DA2 P32-P37 P40/INT4, P41/INT0, P43/INT2 P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/SIN2, P51/SOUT2, P52/SCLK2, P53/SRDY2 P54/CNTR0, P55/CNTR1 P56/PWM P57/INT3 P60/AN0- P67/AN7
Port P2
Data bus I/O D-A conversion output Control signal I/O External interrupt input
CPU mode register AD/DA control register CPU mode register CPU mode register Interrupt edge selection register Serial I/O1 control register UART control register
Port P3
(2) (1) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (3) (14)
Port P4
Input/output, individual bits
CMOS 3-state output CMOS compatible input level
Serial I/O1 function I/O
Serial I/O2 function I/O Port P5 Input/output, individual bits CMOS 3-state output CMOS compatible input level
Serial I/O2 control register
Timer X and Timer Y function I/O PWM output External interrupt input A-D conversion input
Timer XY mode register PWM control register Interrupt edge selection register
Port P6
Input/output, individual bits
CMOS 3-state output CMOS compatible input level
Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
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HARDWARE
FUNCTIONL DESCRIPTION
(1) Ports P0, P1, P2, P32-P37
Direction register
(2) Ports P30, P31
Direction register
Data bus
Port latch
Data bus
Port latch
D-A conversion output DA1 output enable bit (P30) DA2 output enable bit (P31)
(3) Ports P40-P43, P57
Direction register
(4) Port P44
Serial I/O1 enable bit Receive enable bit
Direction register
Data bus
Port latch
Data bus
Port latch
Interrupt input Serial I/O1 input
(5) Port P45
P45/TXD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit
Direction register
(6) Port P46
Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit
Direction register
Data bus
Port latch Data bus Port latch
Serial I/O1 output Serial I/O1 clock output Serial I/O1 external clock input
(7) Port P47
Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit
Direction register
(8) Port P50
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 input
Serial I/O1 ready output
Fig. 12 Port block diagram (single-chip mode) (1)
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FUNCTIONAL DESCRIPTION
(9) Port P51
P51/SOUT2 P-channel output disable bit Serial I/O2 transmit end signal Serial I/O2 port selection bit
Direction register
(10) Port P52
Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 output
Serial I/O2 clock output Serial I/O2 external clock input
(11) Port P53
SRDY2 output enable bit
(12) Ports P54, 55
Direction register Direction register
Data bus Data bus Port latch
Port latch
Pulse output mode Serial I/O2 ready output Timer output CNTR0, CNTR1 Interrupt input
(13) Port P56
PWM output enable bit
(14) Port P6
Direction register Direction register
Data bus Data bus Port latch
Port latch
A-D conversion input PWM output Analog input pin selection bit
Fig. 13 Port block diagram (single-chip mode) (2)
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HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPTS
Interrupts occur by sixteen sources: seven external, eight internal, and one software.
Interrupt operation
When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering.The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter.
Interrupt control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. Table 7. Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 1 Timer 2 CNTR0 CNTR1 Serial I/O2 INT2 INT3 INT4 A-D converter BRK instruction Priority 1 2 3 4 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFF716 FFFA16 FFF816 FFF616
Notes on use
When the active edge of an external interrupt (INT0 to INT4, CNTR0, or CNTR1) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to "0". (4) Enable the external interrupt which is selected.
5 6 7 8 9 10 11 12 13 14 15 16 17
FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16
FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16
Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of serial I/O2 data transfer At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At completion of A-D conversion At BRK instruction execution
Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable)
Non-maskable software interrupt
Note 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.
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FUNCTIONAL DESCRIPTION
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. 14 Interrupt control
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns "0" when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit Not used (returns "0" when read)
0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Serial I/O2 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4 interrupt request bit AD converter interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit
b7
b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit
b7
b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Serial I/O2 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit AD converter interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled
Fig. 15 Structure of interrupt-related registers
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HARDWARE
FUNCTIONAL DESCRIPTION
Timers
The 3802 group has four timers: timer X, timer Y, timer 1, and timer 2. All timers are count down. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1". The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch.
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency divided by 16. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each be selected in one of four operating modes by setting the timer XY mode register. Timer Mode The timer counts f(XIN)/16 in timer mode. Pulse Output Mode Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of the timer reach "0016", the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge switch bit is "0", output begins at " H". If it is "1", output starts at "L". When using a timer in this mode, set the corresponding port P54 ( or port P55) direction register to output mode. Event Counter Mode Operation in event counter mode is the same as in timer mode, except the timer counts signals input through the CNTR0 or CNTR1 pin. Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is "0", the timer counts at the oscillation frequency divided by 16 while the CNTR0 (or CNTR1) pin is at "H". If the CNTR0 (or CNTR1) active edge switch bit is "1", the count continues during the time that the CNTR0 (or CNTR1) pin is at "L". In all of these modes, the count can be stopped by setting the timer X (timer Y) count stop bit to "1". Every time a timer underflows, the corresponding interrupt request bit is set.
b7
b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bit b4b5 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop
Fig. 16 Structure of timer XY register
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FUNCTIONAL DESCRIPTION
Data bus Oscillator f(XIN) Divider 1/16 Pulse width measurement mode P54/CNTR0 pin CNTR0 active edge switch bit "0" "1" Timer mode Pulse output mode Prescaler X (8) Event counter mode CNTR0 active edge switch bit "1" "0" Q Timer X count stop bit To CNTR0 interrupt request bit Timer X (8) To timer X interrupt request bit Prescaler X latch (8) Timer X latch (8)
Q Toggle flip- flop R Timer X latch write pulse Pulse output mode Data bus T
Port P54 direction register
Port P54 latch Pulse output mode
Prescaler Y latch (8) Pulse width measurement mode P55/CNTR1 pin CNTR1 active edge switch bit "0" "1" Timer mode Pulse output mode Prescaler Y (8) Event counter mode CNTR1 active edge switch bit "1" "0" Q Timer Y count stop bit
Timer Y latch (8)
Timer Y (8)
To timer Y interrupt request bit To CNTR1 interrupt request bit
Q Toggle flip- flop R Timer Y latch write pulse Pulse output mode T
Port P55 direction register
Port P55 latch Pulse output mode
Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt request bit
To timer 1 interrupt request bit
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2
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HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
Clock synchronous serial I/O mode
Clock synchronous serial I/O1 mode can be selected by setting the mode selection bit of the serial I/O1 control register to "1". For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 001816).
Data bus Serial I/O1 control register Address 001A16
Address 001816 Receive buffer P44/RXD Receive shift register Shift clock P46/SCLK1
Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
f(XIN) XIN
BRG count source selection bit 1/4
Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4
P47/SRDY1
F/F
Falling-edge detector Shift clock
Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
P45/TXD
Transmit shift register Transmit buffer Address 001816 Data bus
Fig. 18 Block diagram of clock synchronous serial I/O1
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY1 Write pulse to receive/transmit buffer (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 19 Operation of clock synchronous serial I/O1 function
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FUNCTIONAL DESCRIPTION
Asynchronous serial I/O (UART) mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next character is being received.
Data bus Address 001816 Receive buffer OE Character length selection bit P44/RXD STdetector 7 bits 8 bits PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P45/TXD Character length selection bit Transmit buffer Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Receive shift register 1/16 UART control register Address 001B16 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI)
f(XIN)
Fig. 20 Block diagram of UART serial I/O
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HARDWARE
FUNCTIONAL DESCRIPTION
Transmit or receive clock
Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1V
Serial output TXD
ST
D0
D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s)
SP
ST
D0
D1
V
SP Generated at 2nd bit in 2-stop-bit mode
Receive buffer read signal
RBF=0 RBF=1 RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O function
Serial I/O1 control register (SIO1CON) 001A16
The serial I/O control register consists of eight control bits for the serial I/O function.
UART control register (UARTCON) 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/TXD pin.
spectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".
Transmit buffer/Receive buffer register (TB/ RB) 001816
The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0".
Serial I/O1 status register (SIO1STS) 001916
The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re-
Baud rate generator (BRG) 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
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FUNCTIONAL DESCRIPTION
b7
b0
Serial I/O1 status register (SIO1STS : address 0019 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O1 control register (SIO1CON : address 001A 16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinaly I/O pin 1: P47 pin operates as S RDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P44 to P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44 to P47 operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read)
Fig. 22 Structure of serial I/O control registers
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HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O2
The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register.
b7 b0
Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits
b2 b1 b0
Serial I/O2 control register (SIO2CON) 001D16
The serial I/O2 control register contains seven bits which control various serial I/O functions.
0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 Serial I/O2 port selection bit (SM23) 0: I/O port 1: SOUT2,SCLK2 output pin SRDY2 output enable bit (SM24) 0: I/O port 1: SRDY2 output pin Transfer direction selection bit (SM25) 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit (SM26) 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode)
Fig. 23 Structure of serial I/O2 control register
1/8 1/16
Divider
Internal synchronous clock selection bits
XIN
1/32 1/64 1/128 1/256
Data bus
P53 latch "0" Serial I/O2 synchronous clock selection bit SRDY2 Synchronization circuit
SCLK2
"1" "0"
P53/SRDY2
"1" SRDY2 output enable bit
External clock
P52 latch "0"
P52/SCLK2
"1" Serial I/O2 port selection bit P51 latch "0"
Serial I/O counter 2 (3)
Serial I/O2 interrupt request
P51/SOUT2
"1" Serial I/O2 port selection bit
P50/SIN2
Serial I/O shift register 2 (8)
Fig. 24 Block diagram of serial I/O2 function
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FUNCTIONAL DESCRIPTION
Transfer clock (Note 1) Serial I/O2 register write signal
(Note 2)
Serial I/O2 output SOUT2 Serial I/O2 input SIN2
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the S OUT2 pin goes to high impedance after transfer completion.
Fig. 25 Timing of serial I/O2 function
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HARDWARE
FUNCTIONAL DESCRIPTION
PULSE WIDTH MODULATION (PWM)
The 3802 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to "1", operation starts by initializing the PWM output circuit, and pulses are output starting at an "H". If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made.
Data Setting
The PWM output pin also functions as port P56. Set the PWM period by the PWM prescaler, and set the period during which the output pulse is an "H" by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ! (n+1)/f(XIN) = 51 ! (n+1) s (when XIN = 5 MHz) Output pulse "H" period = PWM period ! m/255 = 0.2 ! (n+1) ! m s (when XIN = 5 MHz)
51 ! m ! (n+1) s 255 PWM output T = [51 ! (n+1)] s m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when X IN = 5 MHz)
Fig. 26 Timing of PWM cycle
Data bus
PWM prescaler pre-latch
PWM register pre-latch
Transfer control circuit
PWM prescaler latch Count source selection bit XIN 1/2 "0" "1" PWM prescaler
PWM register latch
Port P56 PWM register
Port P56 latch
PWM enable bit
Fig. 27 Block diagram of PWM function
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FUNCTIONAL DESCRIPTION
b7
b0
PWM control register (PWMCON : address 002B16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) 1: f(XIN)/2 Not used (return "0" when read)
Fig. 28 Structure of PWM control register
A PWM output T PWM register write signal
B
C
B= C T2 T
T (Changes from "A" to "B" during "H" period)
T2
PWM prescaler write signal
(Changes from "T" to "T2" during PWM period)
When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.
Fig. 29 PWM output timing when PWM register or PWM prescaler is changed
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HARDWARE
FUNCTIONAL DESCRIPTION
A-D Converter
The functional blocks of the A-D converter are described below.
[Comparator and Control circuit]
The comparator and control circuit compares an analog input voltage with the comparison voltage, then stores the result in the A-D conversion register. When an A-D conversion is complete, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that the comparator is constructed linked to a capacitor, so set f(XIN) to 500 kHz or more during an A-D conversion.
[A-D conversion register]
The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read.
[AD/DA control register]
The AD/DA control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, and changes to "1" when an A-D conversion ends. Writing "0" to this bit starts the A-D conversion. Bits 6 and 7 are used to control the output of the D-A converter.
b7
b0
AD/DA control register (ADCON : address 003416) Analog input pin selection bits
b2 b1 b0
[Comparison voltage generator]
The comparison voltage generator divides the voltage between AVSS and VREF into 256, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of the ports P60/AN0 to P67/AN7, and inputs the voltage to the comparator.
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0: P60/AN0 1: P61/AN1 0: P62/AN2 1: P63/AN3 0: P64/AN4 1: P65/AN5 0: P66/AN6 1: P67/AN7
AD conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (return "0" When read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled
Fig.30 Structure of AD/DA control register
Data bus
AD/DA control register (Address 0034 16)
b7
b0
3 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 A-D control circuit A-D interrupt request
Channel selector
Comparator
A-D conversion register (Address 0035 16) 8 Resistor ladder
VREF AVSS
Fig. 31 Block diagram of A-D converter
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HARDWARE
FUNCTIONAL DESCRIPTION
D-A Converter
The 3802 group has two internal D-A converters (DA1 and DA2) with 8-bit resolutions. The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from the DA1 or DA2 pin by setting the DA output enable bit to "1". When using the D-A converter, the corresponding port direction register bit (P30/DA1 or P31/DA2) should be set to "0" (input status). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V = VREF ! n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to "0016", the DA output enable bits are cleared to "0", and the P30/DA1 and P31/ DA2 pins are set to input (high impedance). The D-A output is not buffered, so connect an external buffer when driving a low-impedance load. Set VCC to 3.0 V or more when using the D-A converter.
D-A1 conversion register (8) DA1 output enable bit P30/DA1
Data bus
R-2R resistor ladder
D-A2 conversion register (8) DA2 output enable bit P31/DA2
R-2R resistor ladder
Fig. 32 Block diagram of D-A converter
"0" DA1 output enable bit R
R 2R
R 2R
R 2R
R 2R
R 2R
R 2R
2R 2R LSB
P30/DA1
"1" MSB
2R
D-A1 conversion register AVSS VREF
"0"
"1"
Fig. 33 Equivalent connection circuit of D-A converter
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HARDWARE
FUNCTIONAL DESCRIPTION
Reset Circuit
To reset the microcomputer, the RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 4.0 V and 5.5 V), reset is released. Internal operation begin until after 8 to 13 XIN clock cycles are completed. After the reset is completed, the program starts from the address contained in address FFFD16 (highorder byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.6 V for VCC of 3.0 V (Extended operating temperature version : the reset input voltage is less than 0.8 V for VCC of 4.0 V).
Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Port P4 direction register (6) Port P5 direction register (7) Port P6 direction register (8) Serial I/O1 status register (9) Serial I/O1 control register (10) UART control register (000116) * * * (000316) * * * (000516) * * * (000716) * * * (000916) * * * (000B16) * * * (000D16) * * * Register contents 0016 0016 0016 0016 0016 0016 0016
(001916) * * * 1 0 0 0 0 0 0 0 (001A16) * * * 0016
(001B16) * * * 1 1 1 0 0 0 0 0 (001D16) * * * (002016) * * * (002116) * * * (002216) * * * (002316) * * * (002416) * * * (002516) * * * (002616) * * * (002716) * * * (002B16) * * * 0016 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 0016
4.0V Power source 0V voltage 0.8V
(11) Serial I/O2 control register (12) Prescaler 12 (13) Timer 1 (14) Timer 2
Reset input 0V voltage
(15) Timer XY mode register (16) Prescaler X (17) Timer X
1 5 M51953AL 4 0.1  F
VCC RESET
(18) Prescaler Y (19) Timer Y (20) PWM control register (21) AD/DA control register (22) D-A1 conversion register
(003416) * * * 0 0 0 0 1 0 0 0 (003616) * * * (003716) * * * 0016 0016 0016
3
VSS 3802 group
(23) D-A2 conversion register
(24) Interrupt edge selection register (003A16) * * * (25) CPU mode register
(003B16) * * * 0 0 0 0 0 0 V 0 (003C16) * * * (003D16) * * * (003E16) * * * (003F16) * * * 0016 0016 0016 0016
Fig. 34 Example of reset circuit
(26) Interrupt request register 1 (27) Interrupt request register 2 (28) Interrupt control register 1 (29) Interrupt control register 2 (30) Processor status register (31) Program counter
(PS) ! ! ! ! ! 1 ! ! (PCH) Contents of address FFFD16 (PCL) Contents of address FFFC16
Note. ! : Undefined V : The initial values of CM1 are determined by the level at the CNVSS pin. The contents of all other registers and RAM are undefined after a reset, so they must be initialized by software.
Fig. 35 Internal status of microcomputer after reset
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HARDWARE
FUNCTIONAL DESCRIPTION
XIN

RESET
RESETOUT (internal reset) SYNC
Address
?
?
?
?
?
FFFC
FFFD
ADH, ADL Reset address from the vector table
Data XIN: 8 to 13 clock cycles
?
?
?
?
?
ADL
ADH
Notes 1: f(XIN) and f() are in the relationship: f(XIN)=2 * f(). 2: A question mark (?) indicates an undefined status that depends on the previous status.
Fig. 36 Timing of reset
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HARDWARE
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. When the STP status is released, prescaler 12 and timer 1 will start counting and reset will not be released until timer 1 underflows, so set the timer 1 interrupt enable bit to "0" before the STP instruction is executed.
Oscillation control
Stop Mode If the STP instruction is executed, the internal clock  stops at an "H". Timer 1 is set to "0116" and prescaler 12 is set to "FF16". Oscillator restarts when an external interrupt is received, but the internal clock  remains at an "H" until timer 1 underflow. This allows time for the clock circuit oscillation to stabilize. If oscillator is restarted by a reset, no wait time is generated, so keep the RESET pin at an "L" level until oscillation has stabilized. Wait Mode If the WIT instruction is executed, the internal clock  stops at an "H" level, but the oscillator itself does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed.
XIN
XOUT
CIN
COUT
Fig. 37 Ceramic resonator circuit
XIN
XOUT Open
External oscillation circuit
Vcc Vss
Fig. 38 External clock input circuit
Interrupt request
Interrupt disable flag (I) Reset STP instruction
S
Q
S
Q
Q
S
Reset
R
WIT instruction
R
R
STP instruction
 output
ONW pin Single-chip mode 1/2 Rd
Internal clock  ONW control 1/8 Prescaler 12 FF16 0116 Timer 1
Reset or STP instruction
Rf XIN XOUT
Fig. 39 Block diagram of clock generating circuit
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HARDWARE
FUNCTIONAL DESCRIPTION
Processor Modes
Single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits CM0 and CM1 (bits 0 and 1 of address 003B16). In memory expansion mode and microprocessor mode, memory can be expanded externally through ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. Table 8. Functions of ports in memory expansion mode and microprocessor mode Port Name Function Port P0 Outputs low-order byte of address. Port P1 Outputs high-order byte of address. Operates as I/O pins for data D7 to D0 Port P2 (including instruction codes). P30 and P31 function only as output pins (except that the port latch cannot be read). P32 is the ONW input pin. P33 is the RESETOUT output pin. (Note) Port P3 P34 is the  output pin. P35 is the SYNC output pin. P36 is the WR output pin, and P37 is the RD output pin.
000016 000816 004016
SFR area Internal RAM reserved area
000016 000816 004016
SFR area Internal RAM reserved area
044016
V
044016
YYYY16 FFFF16
Internal ROM
FFFF16
Microprocessor mode The shaded areas are external memory areas.
V : YYYY16 is the start address of internal ROM.
Memory expansion mode
Fig. 40 Memory maps in various processor modes
b7
b0
Note: If CNVSS is connected to VSS, the microcomputer goes to single-chip mode after a reset, so this pin cannot be used as the RESETOUT output pin. Single-Chip Mode Select this mode by resetting the microcomputer with CNVSS connected to VSS. Memory Expansion Mode Select this mode by setting the processor mode bits to "01" in software with CNVSS connected to VSS. This mode enables external memory expansion while maintaining the validity of the internal ROM. Internal ROM will take precedence over external memory if addresses conflict. Microprocessor Mode Select this mode by resetting the microcomputer with CNVSS connected to VCC, or by setting the processor mode bits to "10" in software with CNVSS connected to VSS. In microprocessor mode, the internal ROM is no longer valid and external memory must be used.
CPU mode register (CPUM : address 003B16) Processor mode bits
b1 b0
0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Not used (return "0" when read)
Fig. 41 Structure of CPU mode register
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HARDWARE
FUNCTIONAL DESCRIPTION
Bus control with memory expansion
The 3802 group has a built-in ONW function to facilitate access to external memory and I/O devices in memory expansion mode or microprocessor mode. If an "L" level signal is input to the ONW pin when the CPU is in a read or write state, the corresponding read or write cycle is extended by one cycle of . During this extended period, the RD or WR signal remains at "L". This extension period is valid only for writing to and reading from addresses 000016 to 000716 and 044016 to FFFF16 in microprocessor mode, 044016 to YYYY16 in memory expansion mode, and only read and write cycles are extended.
Read cycle
Dummy cycle Write cycle
Read cycle Dummy cycle
Write cycle
 AD15 to AD0 RD WR ONW V V V
V : Period during which ONW input signal is received During this period, the ONW signal must be fixed at either "H" or "L". At all other times, the input level of the ONW signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 043F16, regardless of whether the ONW signal is received.
Fig. 42 ONW function timing
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HARDWARE
NOTE ON PROGRAMMING
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to "1". Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. The SOUT2 pin from serial I/O2 goes to high impedance after transmission is completed.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before executing a BBC or BBS instruction.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is at least 500 kHz during an A-D conversion. (If the ONW pin has been set to "L", the A-D conversion will take twice as long to match the longer bus cycle, and so f(XIN) must be at least 1 MHz.) Do not execute the STP or WIT instruction during an A-D conversion.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC.
D-A Converter
The accuracy of the D-A converter becomes poor rapidly under the VCC = 3.0 V or less condition.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock  by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock  is half of the XIN frequency. When the ONW function is used in modes other than single-chip mode, the frequency of the internal clock  may be one fourth the XIN frequency.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register.
Memory Expansion Mode
The memory expansion mode is not available in the following microcomputers. * M38024M6-XXXSP * M38024M6-XXXFP
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers.
Memory Expansion Mode and Microprocessor Mode
Execute the LDM or STA instruction for writing to port P3 (address 000616) in memory expansion mode and microprocessor mode. Set areas which can be read out and write to port P3 (address 000616) in a memory, using the read-modify-write instruction (SEB, CLB).
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HARDWARE
DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 9. Programming adapter Package 64P4B, 64S1B 64P6N 64D0 Name of Programming Adapter PCA4738S-64A PCA4738F-64A PCA4738L-64A
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 35 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150C for 40 hours)
Verification with PROM programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 43 Programming and testing of One Time PROM version
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FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt 3802 group permits interrupts on the basis of 16 sources. It is vector interrupts with a fixed priority system. Accordingly, when two or more interrupt
requests occur during the same sampling, the higherpriority interrupt is accepted first. This priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to "Table 10."
Table 10. Interrupt sources, vector addresses and interrupt priority Vector addresses Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Interrupt sources High-order Low-order Reset (Note) INT0 interrupt INT1 interrupt Serial I/O1 receive interrupt Serial I/O1 transmit interrupt Timer X interrupt Timer Y interrupt Timer 1 interrupt Timer 2 interrupt CNTR0 interrupt CNTR1 interrupt Serial I/O2 interrupt INT2 interrupt INT3 interrupt INT4 interrupt A-D conversion interrupt BRK instruction interrupt FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected Remarks
STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Non-maskable software interrupt
Note: Reset functions in the same way as an interrupt with the highest priority.
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HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 44 shows a timing chart after an interrupt occurs, and Figure 45 shows the time up to execution of the interrupt processing routine.
SYNC RD WR Address bus Data bus
SYNC BL, BH AL, AH SPS
PC Not used
S, SPS
S-1, SPS S-2, SPS
BL AL
BH
AL, AH AH
PCH PCL
PS
: CPU operation code fetch cycle : Vector address of each interrupt : Jump destination address of each interrupt : "0016" or "0116"
Fig. 44 Timing chart after an interrupt occurs
Generation of interrupt request
Start of interrupt processing
Main routine
Waiting time for post-processing of pipeline
Stack push and Vector fetch
Interrupt processing routine
0 to 16 T cycles
2 cycles
5 cycles
7 to 23 cycles (At performing 8.0 MHz, 1.75 s to 5.75 s) T : at execution of DIV instruction (16 cycles) Fig. 45 Time up to execution of the interrupt processing routine
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FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter A-D conversion is started by setting AD conversion completion bit to "0." During A-D conversion, internal operations are performed as follows. 1. After the start of A-D conversion, A-D conversion register goes to "0016." 2. The highest-order bit of A-D conversion register is set to "1," and the comparison voltage Vref is input to the comparator. Then, Vref is compared with analog input voltage VIN. 3. As a result of comparison, when Vref < VIN, the highest-order bit of A-D conversion register be comes "1." When Vref > VIN, the highest-order bit becomes "0." By repeating the above operations up to the lowestorder bit of the A-D conversion register, an analog value converts into a digital value. A-D conversion completes at 50 clock cycles (12.5  s at f(XIN) = 8.0 MHz) after it is started, and the result of the conversion is stored into the A-D conversion register. Concurrently with the completion of A-D conversion, A-D conversion interrupt request occurs, so that the AD conversion interrupt request bit is set to "1."
Relative formula for a reference voltage VREF of A-D converter and Vref When n = 0 When n = 1 to 255 Vref = 0 Vref = VREF ! (n - 0.5) 256 n : the value of A-D converter (decimal numeral)
Table 11. Change of A-D conversion register during A-D conversion Change of A-D conversion register At start of conversion First comparison Second comparison Third comparison
V
Value of comparison voltage (Vref) 0 VREF 2 VREF 2 VREF 2 - VREF 512   VREF 4 VREF 4 -  VREF 512 VREF 8 - VREF 512
0 1 1 1
V
0 0 1 2
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
V
After completion of eighth comparison V1: V3: V5: V7: A A A A result result result result of of of of the the the the
A result of A-D conversion
V
1
V
2
V
3
V
4
V
5 A A A A
V
6
V
7
V
8 the the the the second comparison fourth comparison sixth comparison eighth comparison
first comparison third comparison fifth comparison seventh comparison
V2: V4: V6: V8:
result result result result
of of of of
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HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 46 shows A-D conversion equivalent circuit, and Figure 47 shows A-D conversion timing chart.
VCC about 2 k AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
VSS VIN Sampling clock
VCC AVSS
C Chopper amplifier
A-D conversion register
b2 b1 b0
AD/DA control register VREF
Build-in D-A converter
A-D conversion interrupt request
Vref
Reference clock
AVSS Fig. 46 A-D conversion equivalent circuit
Write signal for AD/DA control register
50 cycles
AD conversion completion bit
Sampling clock
Fig. 47 A-D conversion timing chart
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3802 GROUP USER'S MANUAL
CHAPTER 2 APPLICATION
2.1 2.2 2.3 2.4 2.5 2.6 2.7 I/O port Timer Serial I/O PWM A-D converter Processor mode Reset
APPLICATION
2.1 I/O port
2.1 I/O port
2.1.1 Memory map of I/O port
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D)
Fig. 2.1.1 Memory map of I/O port related registers
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3802 GROUP USER'S MANUAL
APPLICATION
2.1 I/O port
2.1.2 Related registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6) [Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16]
B 0 Port Pi0 1 Port Pi1
Name
q
Function
In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins
At reset
RW
? ? ? ? ? ? ? ?
q
2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6) [Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16]
B
Name
Function
0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
At reset
RW
! ! ! ! ! ! ! !
0 Port Pi direction register 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6)
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APPLICATION
2.1 I/O port
2.1.3 Handling of unused pins Table 2.1.1 Handling of unused pins (in single-chip mode) Name of Pins/Ports P0, P1, P2, P3, P4, P5, P6 Handling * Set to the input mode and connect to VCC or VSS through a resistor of 1 k to 10 k . * Set to the output mode and open at "L" or "H." Connect to VSS(GND) or open. Connect to VSS(GND). Open (only when using external clock).
VREF AVSS XOUT
Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) Name of Pins/Ports P30, P31 P4, P5, P6 Handling Open * Set to the input mode and connect to VCC or VSS through a resistor of 1 k to 10 k . * Set to the output mode and open at "L" or "H." Connect to VSS(GND) or open. Connect to VCC through a resistor of 1 k to 10 k . Open Open Open Connect to VSS(GND). Open (only when using external clock).
VREF
____
ONW
_________
RESETOUT
SYNC AVSS XOUT
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3802 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
2.2 Timer
2.2.1 Memory map of timer
002016 002116 002216 002316 002416 002516 002616 002716 003C16 003D16 003E16 003F16
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of timer related registers
3802 GROUP USER'S MANUAL
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APPLICATION
2.2 Timer
2.2.2 Related registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY) [Address : 2016, 2416, 2616]
B 0 1 2 3 4 5 6 7
Function
q q q
At reset
RW
The count value of each prescaler is set. The value set in this register is written to both the prescaler and the prescaler latch at the same time. When the prescaler is read out, the value (count value) of the prescaler is read out.
1 1 1 1 1 1 1 1
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 2116]
B 0 1 2 3 4 5 6 7
Function
q q q
At reset
RW
The count value of the Timer 1 is set. The value set in this register is written to both the Timer 1 and the Timer 1 latch at the same time. When the Timer 1 is read out, the value (count value) of the Timer 1 is read out.
1 0 0 0 0 0 0 0
Fig. 2.2.3 Structure of Timer 1
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3802 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2), Timer X (TX), Timer Y (TY) [Address : 2216, 2516, 2716]
B 0 1 2 3 4 5 6 7
q q q
Function
The count value of each timer is set. The value set in this register is written to both the Timer and the Timer latch at the same time. When the Timer is read out, the value (count value) of the Timer is read out.
At reset
RW
1 1 1 1 1 1 1 1
Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y
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APPLICATION
2.2 Timer
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer XY mode register (TM) [Address : 2316]
Name B 0 Timer X operating mode bit
Function
b1 b0
At reset
RW
0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 1 : Pulse width measurement mode It depends on the operating mode 2 CNTR0 active edge switch bit of the Timer X (refer to Table 2.2.1). 0 : Count start 3 Timer X count stop bit 1 : Count stop
0 0 0 0 0 0 0 0
4 Timer Y operating mode bit
0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 5 1 1 : Pulse width measurement mode 6 CNTR1 active edge switch bit It depends on the operating mode of the Timer Y (refer to Table 2.2.1). 0 : Count start 7 Timer Y count stop bit 1 : Count stop
b5 b4
Fig. 2.2.5 Structure of Timer XY mode register
Table. 2.2.1 Function of CNTR0/CNTR1 edge switch bit Operating mode of Timer X/Timer Y Timer mode Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6) "0" "1" Pulse output mode "0" "1" Event counter mode "0" "1" Pulse width measurement mode "0" "1" * Generation of CNTR0/CNTR1 interrupt request : Falling (No effect on timer count) * Generation of CNTR0/CNTR1 interrupt request : Rising (No effect on timer count) * Start of pulse output : From "H" level * Generation of CNTR0/CNTR1 interrupt request : Falling * Start of pulse output : From "L" level * Generation of CNTR0/CNTR1 interrupt request : Rising * Timer X/Timer Y : Count of rising edge * Generation of CNTR0/CNTR1 interrupt request : Falling * Timer X/Timer Y : Count of falling edge * Generation of CNTR0/CNTR1 interrupt request : Rising * Timer X/Timer Y : Measurement of "H" level width * Generation of CNTR0/CNTR1 interrupt request : Falling * Timer X/Timer Y : Measurement of "L" level width * Generation of CNTR0/CNTR1 interrupt request : Rising edge edge
edge edge edge edge edge edge
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3802 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address : 3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T T
0 INT0 interrupt request bit 1 INT1 interrupt request bit 2 Serial I/O1 receive interrupt
request bit
0 0 0 0 0 0 0 0
3 Serial I/O1 transmit interrupt
request bit bit
4 Timer X interrupt request 5 Timer Y interrupt request
bit 6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
T "0" is set by software, but not "1."
Fig. 2.2.6 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name B 0 CNTR0 interrupt request bit 1 CNTR1 interrupt request bit 2 Serial I/O2 interrupt request
bit
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T !
0 0 0 0 0 0 0 0
3 INT2 interrupt request bit 4 INT3 interrupt request bit 5 INT4 interrupt request bit 6 AD conversion interrupt
request bit
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0." T "0" is set by software, but not "1."
Fig. 2.2.7 Structure of Interrupt request register 2
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APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1 interrupt enable bit
enable bit 3 Serial I/O1 transmit interrupt enable bit 4 Timer X interrupt enable bit
0 0 0 0 0 0 0 0
2 Serial I/O1 receive interrupt
5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit 7 Timer 2 interrupt enable bit
Fig. 2.2.8 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name B CNTR0 interrupt enable bit 0
Function
At reset
RW
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 CNTR1 interrupt enable bit 1 : Interrupt enabled 0 : Interrupt disabled 2 Serial I/O2 interrupt enable bit 1 : Interrupt enabled 0 : Interrupt disabled 3 INT2 interrupt enable bit 1 : Interrupt enabled
0 0 0 0 0 0 0 0
4 INT3 interrupt enable bit 5 INT4 interrupt enable bit 6 AD conversion interrupt
enable bit
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
7 Fix this bit to "0."
Fig. 2.2.9 Structure of Interrupt control register 2
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3802 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
2.2.3 Timer application examples (1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2) The Timer count stop bit is set to "0" after setting a count value to a timer. Then a timer interrupt request occurs after a certain period. [Use] * Generation of an output signal timing * Generation of a waiting time [Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2) The value of a timer latch is automatically written to a corresponding timer every time a timer underflows, and each cyclic timer interrupt request occurs. [Use] * Generation of cyclic interrupts * Clock function (measurement of 250m second) * Control of a main routine cycle
Application example 1
[Function 3] Output of Rectangular waveform (Timer X, Timer Y) The output level of the CNTR pin is inverted every time a timer underflows (Pulse output mode). [Use] * A piezoelectric buzzer output Application example 2 * Generation of the remote-control carrier waveforms [Function 4] Count of External pulse (Timer X, Timer Y) External pulses input to the CNTR pin are selected as a timer count source (Event counter mode). [Use] * Measurement of frequency Application example 3 * Division of external pulses. * Generation of interrupts in a cycle based on an external pulse. (count of a reel pulse) [Function 5] Measurement of External pulse width (Timer X, Timer Y) The "H" or "L" level width of external pulses input to CNTR pin is measured (Pulse width measurement mode). [Use] * Measurement of external pulse frequency (Measurement of pulse width of FG pulse V generated by motor) Application example 4 * Measurement of external pulse duty (when the frequency is fixed)
VFG pulse : Pulse used for detecting the motor speed to control the motor speed.
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APPLICATION
2.2 Timer
(2) Timer application example 1 : Clock function (measurement of 250 ms) Outline : The input clock is divided by a timer so that the clock counts up every 250 ms. Specifications : * The clock f(XIN) = 4.19 MHz (2 22 Hz) is divided by a timer. * The clock is counted at intervals of 250 ms by the Timer X interrupt. Figure 2.2.10 shows a connection of timers and a setting of division ratios, Figures 2.2.11 show a setting of related registers, and Figure 2.2.12 shows a control procedure.
Fixed
Prescaler X
Timer X
Timer X interrupt request bit The clock is divided by 4 by software.
f(XIN) = 4.19 MHz
1/16
1/256
1/256
0 or 1
250 ms
1/4
1 second
0 : No interrupt request 1 : Interrupt request
Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function]
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3802 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
Timer XY mode register (Address : 2316)
b7 b0
TM
1
00
Timer X operating mode bits : Timer mode Timer X count stop bit : Count stop Set to "0" at starting to count.
Prescaler X (Address : 2416)
b7 b0
PREX
b7
255 Timer X (Address:2516)
b0
Set "division ratio - 1"
TX
255
Interrupt control register 1 (Address : 3E16)
b7 b0
ICON1
1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16)
b7 b0
IREQ1
0
Timer X interrupt request bit (becomes "1" every 250 ms)
Fig. 2.2.11 Setting of related registers [Clock function]
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APPLICATION
2.2 Timer
Control procedure : Figure 2.2.12 shows a control procedure.
RESET
q
X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SEI TM XXXX1X002 (Address : 2316) ICON1 (Address : 3E16), bit4 1 PREX (Address : 2416) TX (Address : 2516) TM CLI
q
All interrupts : Disabled Timer X : Timer mode Timer X interrupt : Enabled Set "division ratio - 1" to the Prescaler X and Timer X. Timer X count : Operating Interrupts : Enabled
[Processing for completion of setting clock] (Note 1)
Fig. 2.2.12 Control procedure [Clock function]
.
q q
.
256 - 1 256 - 1 0
q
.
(Address : 2316), bit3
q
.
q
q
Main processing
When restarting the clock from zero second after completing to set the clock, re-set timers.
Note 1: This processing is performed only at completing to set the clock.
PREX (Address : 2416) TX (Address : 2516) IREQ1 (Address : 3C16), bit4
.
256 - 1 256 - 1 0 Timer X interrupt processing routine CLT (Note 2) CLD (Note 3) Push register to stack
q
Note 2: When using the Index X mode flag (T). Note 3: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack.
Clock stop? N Clock count up (1/4 second-year)
Y
q
Check if the clock has already been set.
q
Count up the clock.
Pop registers
q
Pop registers which is pushed to stack
RTI
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3802 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
(3) Timer application example 2 : Piezoelectric buzzer output Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. Specifications : * The rectangular waveform resulting from dividing clock f(XIN) = 4.19 MHz into about 2 kHz (2048 Hz) is output from the P54/CNTR0 pin. * The level of the P54/CNTR0 pin fixes to "H" while a piezoelectric buzzer output is stopped. Figure 2.2.13 shows an example of a peripheral circuit, and Figure 2.2.14 shows a connection of the timer and setting of the division ratio.
The "H" level is output while a piezoelectric buzzer output is stopped. CNTR0 output
3802 group
P54/CNTR0 PiPiPi. 244  s 244  s Set a division ratio so that the underflow output cycle of the Timer X becomes this value.
Fig. 2.2.13 Example of a peripheral circuit
Fixed f(XIN) = 4.19 MHz
Prescaler X
Timer X
Fixed
1/16
1
1/64
1/2
CNTR0
Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]
3802 GROUP USER'S MANUAL
2-15
APPLICATION
2.2 Timer
Timer XY mode register (Address : 2316)
b7 b0
TM
1001
Timer X operating mode bits : Pulse output mode CNTR0 active edge switch bit : Output from the "H" level Timer X count stop bit : Count Stop Set to "0" at starting to count.
Timer X (Address : 2516)
b7
b0
TX
63 Prescaler X (Address : 2416)
b7 b0
Set "division ratio - 1"
PREX
0
Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output]
Control procedure : Figure 2.2.16 shows a control procedure.
RESET Initialization P5 P5D
qX
: This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
0 ICON1(Address : 3E16), bit4 XXXX10012 (Address : 2316) TM (Address : 2516) TX PREX (Address : 2416) 64 - 1 1-1
Output unit
During stopping outputting a piezoelectric buzzer
Fig. 2.2.16 Control procedure [Piezoelectric buzzer output]
.
(Address : 0A16), bit4 1 (Address : 0B16) XXX1XXXX2
q q
.
q
Timer X interrupts : Disabled The CNTR0 output is stopped at this point (stop outputting a piezoelectric buzzer). Set "division ratio - 1" to the Prescaler X and Timer X.
.
Main processing The piezoelectric buzzer request occured in the main processing is processed in the output unit.
q
A piezoelectric buzzer is requested? N
Y
TM (Address : 2316), bit3 TX (Address : 2516)
1 64 -1
TM (Address : 2316), bit3
0
During outputting a piezoelectric buzzer
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APPLICATION
2.2 Timer
(4) Timer application example 3 : Measurement of frequency Outline : The following two values are compared for judging if the frequency is within a certain range. * A value counted a pulse which is input to P55/CNTR1 pin by a timer. * A referance value Specifications : * The pulse is input to the P55/CNTR1 pin and counted by the Timer Y. * A count value is read out at the interval of about 2 ms (Timer 1 interrupt interval : 244  s ! 8). When the count value is 28 to 40, it is regarded the input pulse as a valid. * Because the timer is a down-counter, the count value is compared with 227 to 215 V . V227 to 215 = 255 (initialized value of counter) - 28 to 40 (the number of valid value). Figure 2.2.17 shows a method for judging if input pulse exists, and Figure 2.2.18 shows a setting of related registers.
Input pulse
****
****
****
71.4  s or more (14 kHz or less) Invalid
71.4  s (14 kHz) Valid
50  s (20 kHz)
50  s or less (20 kHz or more) Invalid
2 ms = 28 counts 71.4  s
2 ms 50  s
= 40 counts
Fig 2.2.17 A method for judging if input pulse exists
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APPLICATION
2.2 Timer
Timer XY mode register (Address : 2316)
b7 b0
TM
1110
Timer Y operating mode bit : Event counter mode CNTR1 active edge switch bit : Count at falling edge Timer Y count stop bit : Count stop Set to "0" at starting to count.
Prescaler 12 (Address : 2016)
b7 b0
PRE12
63
Timer 1 (Address : 2116)
b7 b0
T1
7
Set "division ratio - 1"
Prescaler Y (Address : 2616)
b7 b0
PREY
0 Timer Y (Address : 2716)
b7 b0
TY
255
Set "255" to this register immediately before counting pulse. (After a certain time, this value is decreased by the number of input pulses)
Interrupt control register 1 (Address : 3E16)
b7 b0
ICON1
10
Timer Y interrupt enable bit : Interrupt disabled Timer 1 interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16)
b7 b0
IREQ1
0
Judgment of Timer Y interrupt request bit (When this bit is set to "1" at reading out the count value of the Timer Y (address : 2716), 256 pulses or more are input (at setting 255 to the Timer Y).)
Fig. 2.2.18 Setting of related registers [Measurement of frequency]
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3802 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
Control procedure : Figure 2.2.19 shows a control procedure.
RESET Initialization
qX : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
q
All interrupts : Disabled Timer Y : Event counter mode (Count at falling edge of pulse input from CNTR1 pin)
SEI 1110XXXX2 TM (Address : 2316) PRE12 (Address : 2016) 64-1 T1 8-1 (Address : 2116) PREY (Address : 2616) 1-1 TY 256-1 (Address : 2716) ICON1 (Address : 3E16), bit6 1 TM CLI
.
q
q
q
(Address : 2316), bit7
0
q q
Set the division ratio so that the Timer 1 interrupt occurs every 2 ms. Timer 1 interrupt : Enabled Timer Y count : Start Interrupts : Enabled
.
.
1
~ ~
Timer 1 interrupt processing routine CLT (Note 1) CLD (Note 2) Push register to stack Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack. When the count value is 256 or more, the processing is performed as out of range. Read the count value. Store the count value in the accumulator (A).
q
IREQ1 (Address : 3C16), bit5? 0 (A) TY (Address : 2716)
q
q q
214 < (A) < 228? Out of range Fpulse 0
In range
q
q
Compare the count value read with the reference value. Store the comparison result in flag Fpulse. 1
Fpulse
(Address : 2716) TY IREQ1 (Address : 3C16), bit5
256 - 1 0
q
q
Initialize the count value. Set the Timer Y interrupt request bit to "0."
Processing for a result of judgment
Pop registers
q
Pop registers which is pushed to stack.
RTI
Fig. 2.2.19 Control procedure [Measurement of frequency]
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APPLICATION
2.2 Timer
(5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor Outline : The "H" level width of a pulse input to the P54/CNTR0 pin is counted by Timer X. An underflow is detected by Timer X interrupt and an end of the input pulse "H" level is detected by CNTR0 interrupt. Specifications : * The "H" level width of a FG pulse input to the P54/CNTR0 pin is counted by Timer X. (Example : When the clock frequency is 4.19 MHz, the count source would be 3.8  s that is obtained by dividing the clock frequency by 16. Measurement can be made up to 250 ms in the range of FFFF16 to 000016.) Figure 2.2.20 shows a connection of the timer and a setting of the division ration, and Figure 2.2.21 shows a setting of related registers.
Fixed f(XIN) = 4.19 MHz
Prescaler X
Timer X
Timer X interrupt request bit
1/16
1/256
1/256
0 or 1
250 ms 0 : No interrupt request 1 : Interrupt request
Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width]
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3802 GROUP USER'S MANUAL
APPLICATION
2.2 Timer
Timer XY mode register (Address : 2316)
b7 b0
TM
10 11
Timer X operating mode bits : Pulse width measurement mode CNTR0 active edge switch bit : Count "H" level width Timer X count stop bit : Count stop Set to "0" at starting to count.
Prescaler X (Address : 2416)
b7 b0
PREX
255 Timer X (Address : 2516)
b7 b0
Set "division ratio - 1"
TX
255
Interrupt control register 1 (Address : 3E16)
b7 b0
ICON1
1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register (Address : 3C16)
b7 b0
IREQ1
0
Timer X interrupt request bit (This bit is set to "1" at underflow of Timer X.)
Interrupt control register 2 (Address : 3F16)
b7 b0
ICON2
1
CNTR0 interrupt enable bit : Interrupt enabled
Interrupt request register 2 (Address : 3D16)
b7 b0
IREQ2
0
CNTR0 interrupt request bit (This bit is set to "1" at completion of inputting "H" level signal.)
Fig. 2.2.21 Setting of related registers [Measurement of pulse width]
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APPLICATION
2.2 Timer
Figure 2.2.22 shows a control procedure.
RESET Initialization SEI TM PREX TX ICON1 IREQ1 ICON2 IREQ2 TM
q
X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
q
All interrupts : Disabled Timer X : Pulse width measurement mode (Count "H" level width of pulse input from CNTR0 pin.) Set the division ratio so that the Timer X interrupt occurs every 250 ms. Timer X interrupt : Enabled CNTR0 interrupt : Enabled
CLI
(A) Result of pulse width measurement low-order 8-bit (A) Result of pulse width measurement high-order 8-bit PREX (Address : 2416) TX (Address : 2516)
Fig. 2.2.22 Control procedure [Measurement of pulse width]
.
(Address : 2316) (Address : 2416) (Address : 2516) (Address : 3E16), bit4 (Address : 3C16), bit4 (Address : 3F16), bit0 (Address : 3D16), bit0 (Address : 2316), bit3 XXXX10112 256-1 256-1 1 0 1 0 0
q q q q
. .
q
Timer X count : Operating Interrupts : Enabled
q
~ ~
Timer X interrupt processing routine Processing for error RTI
q
Error occurs
CNTR0 interrupt processing routine CLT (Note 1) CLD (Note 2) Push register to stack
Note 1:When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D).
q
Push the register used in the interrupt processing routine into the stack.
PREX Inversion of (A) TX Inversion of (A) 256 - 1 256- 1
q
A count value is read out and stored to RAM.
q
Set the division ratio so that the Timer X interrupt occurs every 250 ms.
Pop registers
q
Pop registers which is pushed to stack.
RTI
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APPLICATION
2.3 Serial I/O
2.3 Serial I/O
2.3.1 Memory map of serial I/O
001816 001916 001A16 001B16 001C16 001D16 001F16 003A16 003C16 003D16 003E16 003F16
Transmit/Receive buffer register (TB/RB ) Serial I/O1 status register (SIO 1STS) Serial I/O1 cont rol register (SIO 1CON) UART control register (UA RT CON)
Baud rate generator (BR G )
Serial I/O2 cont rol register (SIO2CO N) Serial I/O2 register (SIO2 ) Interrupt edge select ion register (INT EDGE) Interrupt request register 1 (IREQ 1) Interrupt request register 2 (IREQ 2)
Interrupt cont rol register 1 (ICON1)
Interrupt cont rol register 2 (ICON2)
Fig. 2.3.1 Memory map of serial I/O related registers
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APPLICATION
2.3 Serial I/O
2.3.2 Related registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816] Function B 0 A transmission data is written to or a receive data is read out
from this buffer register.
At reset
RW
? ? ? ? ? ? ? ?
1 * At writing : a data is written to the Transmit buffer register. 2 3 4 5 6 7
* At reading : a content of the Receive buffer register is read out.
Note: A content of the transmit buffer register cannot be read out. A data cannot be written to the receive buffer register.
Fig. 2.3.2 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 status register (SIO1STS) [Address : 1916]
Name B Transmit buffer empty flag 0
(TBE)
Function
0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : (OE) (PE) (FE) = 0 1 : (OE) (PE) (FE) = 1
At reset
0 0 0 0 0 0 0 1
RW ! ! ! ! ! ! ! !
1 Receive buffer full flag (RBF) 2 Transmit shift register shift
completion flag (TSC)
3 Overrun error flag (OE) 4 Parity error flag (PE) 5 Framing error flag (FE) 6 Summing error flag (SE)
7 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is "0."
Fig. 2.3.3 Structure of Serial I/O1 status register
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3802 GROUP USER'S MANUAL
APPLICATION
2.3 Serial I/O
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON) [Address : 1A16]
B
Name
Function
At reset
RW
0 BRG count source selection bit (CSS) 1
2 3 4 5 6 7
0 : f(XIN) 1 : f(XIN)/4 Serial I/O1 synchronous clock At selecting clock synchronous serial I/O selection bit (SCS) 0 : BRG output divided by 4 1 : External clock input At selecting UART 0 : BRG output divided by 16 1 : External clock input divided by 16 SRDY1 output enable bit 0 : I/O port (P47) (SRDY) 1 : SRDY1 output pin 0 : Transmit buffer empty Transmit interrupt 1 : Transmit shift operating completion source selection bit (TIC) 0 : Transmit disabled Transmit enable bit (TE) 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled 0 : UART Serial I/O1 mode 1 : Clock synchronous serial I/O selection bit (SIOM) Serial I/O1 enable bit (SIOE) 0 : Serial I/O1 disabled (P44-P47 : I/O port) 1 : Serial I/O1 enabled (P44-P47 : Serial I/O function pin)
0 0
0 0 0 0 0 0
Fig. 2.3.4 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address : 1B16]
B 0 1 2 3 4 5 6 7
Name
Character length selection bit (CHAS) Parity enable bit (PARE) Parity selection bit (PARS) Stop bit length selection bit (STPS) P45/TxD P-channel output disable bit (POFF)
Function
At reset
RW
0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : Even parity 1 : Odd parity 0 : 1 stop bit 1 : 2 stop bits In output mode 0 : CMOS output 1 : N-channel open-drain output Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "1."
0 0 0 0 0 1 1 1
Fig. 2.3.5 Structure of UART control register
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2.3 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C16]
B
Function
At reset
RW
0 A count value of Baud rate generator is set. 1 2 3 4 5 6 7
? ? ? ? ? ? ? ?
Fig. 2.3.6 Structure of Baud rate generator
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 control register (SIO2CON) [Address : 1D16]
Name B Internal synchronous clock 0
selection bits
Function
b2 b1 b0
At reset
RW
0 0 0 0 0 0 0 0
1 2 3 Serial I/O2 port selection bit 4 5 6 7
0 0 0 0 1 1
0 0 1 1 1 1
0 : f(XIN)/8 1 : f(XIN)/16 0 : f(XIN)/32 1 : f(XIN)/64 0 : f(XIN)/128 1 : f(XIN)/256
0 : I/O port (P51, P52) 1 : SOUT2, SCLK2 output pin 0 : I/O port (P53) SRDY2 output enable bit 1 : SRDY2 output pin Transfer direction selection bit 0 : LSB first 1 : MSB first Serial I/O2 synchronous clock 0 : External clock 1 : Internal clock selection bit In output mode P51/SOUT2 P-channel 0 : CMOS output output disable bit
1 : N-channel open-drain output
Fig. 2.3.7 Structure of Serial I/O2 control register
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2.3 Serial I/O
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 register (SIO2) [Address : 1F16]
B
Function
At reset
RW
0 A shift register for serial transmission and reception. q At transmitting : Set a transmission data. 1 q At receiving : Store a reception data. 2 3 4 5 6 7
? ? ? ? ? ? ? ?
Fig. 2.3.8 Structure of Serial I/O2 register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A16]
Name B INT0 interrupt edge 0
selection bit
Function
0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active
At reset
RW
0 0 0 0 0 0 0 0
1 INT1 interrupt edge 2 3 4 5 6 7
selection bit Nothing is allocated for this bit. This is a write disabled bit.When this bit is read out, the value is "0." INT2 interrupt edge 0 : Falling edge active selection bit 1 : Rising edge active 0 : Falling edge active INT3 interrupt edge 1 : Rising edge active selection bit INT4 interrupt edge 0 : Falling edge active selection bit 1 : Rising edge active Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0."
Fig. 2.3.9 Structure of Interrupt edge selection register
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2.3 Serial I/O
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address : 3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T T
0 INT0 interrupt request bit 1 INT1 interrupt request bit 2 Serial I/O1 receive interrupt
request bit 3 Serial I/O1 transmit interrupt request bit
0 0 0 0 0 0 0 0
4 Timer X interrupt request bit
bit
5 Timer Y interrupt request bit 6 Timer 1 interrupt request bit 7 Timer 2 interrupt request bit
T "0" is set by software, but not "1."
Fig. 2.3.10 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name B 0 CNTR0 interrupt request bit 1 2 3 4 5 6
Function
At reset
RW
T T T T T T T !
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request CNTR1 interrupt request bit 1 : Interrupt request Serial I/O2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request INT2 interrupt request bit 1 : Interrupt request 0 : No interrupt request INT3 interrupt request bit 1 : Interrupt request 0 : No interrupt request INT4 interrupt request bit 1 : Interrupt request 0 : No interrupt request AD conversion interrupt 1 :Interrupt request request bit When this bit is read out, the value is "0."
0 0 0 0 0 0 0 0
7 Nothing is allocated for this bit. This is a write disabled bit.
T "0" is set by software, but not "1."
Fig. 2.3.11 Structure of Interrupt request register 2
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2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1 interrupt enable bit 2 Serial I/O1 receive interrupt
enable bit 3 Serial I/O1 transmit interrupt enable bit
0 0 0 0 0 0 0 0
4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit 7 Timer 2 interrupt enable bit
Fig. 2.3.12 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name B 0 CNTR0 interrupt enable bit
Function
At reset
RW
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 CNTR1 interrupt enable bit 1 : Interrupt enabled 0 : Interrupt disabled 2 Serial I/O2 interrupt enable bit 1 : Interrupt enabled
0 0 0 0 0 0 0 0
3 INT2 interrupt enable bit 4 INT3 interrupt enable bit 5 INT4 interrupt enable bit 6 AD conversion interrupt
enable bit 7 Fix this bit to "0."
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
Fig. 2.3.13 Structure of Interrupt control register 2
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2.3 Serial I/O
2.3.3 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin There are connection examples using a clock synchronous serial I/O mode. Figure 2.3.14 shows connection examples of a peripheral IC equipped with the CS pin.
(1) Only transmission (using the RXD pin as an I/O port)
(2) Transmission and reception
Port SCLK TXD 3802 group
CS CLK DATA Peripheral IC (OSD controller etc.)
Port SCLK TXD RXD 3802 group
CS CLK IN OUT Peripheral IC (E2 PROM etc.)
(3) Transmission and reception (Pins RXD and TXD are connected) (Pins IN and OUT in peripheral IC are connected) Port SCLK TXD RXD 3802 group T1 CS CLK IN OUT Peripheral 2 (E PROM etc.) IC T2
(4) Connecting ICs
Port SCLK TXD RXD Port 3802 group
CS CLK IN OUT Peripheral IC 1
T1:
Select an N-channel open-drain output control of TXD pin. 2: Use such OUT pin of peripheral IC as an N-channel opendrain output in high impedance during receiving data.
CS CLK IN OUT Peripheral IC 2
Notes1: "Port" is an output port controlled by software. 2: Use SOUT and SIN instead of TXD and RXD in the serial I/O2.
Fig. 2.3.14 Serial I/O connection examples (1)
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2.3 Serial I/O
(2) Connection with microcomputer Figure 2.3.15 shows connection examples of the other microcomputers.
(1) Selecting an internal clock
(2) Selecting an external clock
SCLK TXD RXD 3802 group
CLK IN OUT Microcomputer
SCLK TXD RXD 3802 group
CLK IN OUT Microcomputer
(3) Using the SRDY siganl output function (Selecting an external clock)
(4) Using UART T
SRDY
RDY CLK IN OUT Microcomputer 3802 group Microcomputer TXD RXD RXD TXD
SCLK TXD RXD 3802 group
T: UART can not be used in the serial I/O2. Note: Use SOUT and SIN instead of TXD and RXD in the serial I/O2.
Fig. 2.3.15 Serial I/O connection examples (2)
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2.3 Serial I/O
2.3.4 Setting of serial I/O transfer data format A clock synchronous or clock asynchronous (UART) is selected as a data format of the serial I/O1. The serial I/O2 operates in a clock synchronous. Figure 2.3.16 shows a setting of serial I/O transfer data format.
1ST-8DATA-1SP
ST LSB MSB SP
1ST-7DATA-1SP
ST LSB MSB SP
1ST-8DATA-1PAR-1SP
ST LSB MSB PAR SP
1ST-7DATA-1PAR-1SP
ST LSB MSB PAR SP
UART
1ST-8DATA-2SP
ST LSB MSB 2SP
1ST-7DATA-2SP
ST LSB MSB 2SP
Serial I/O1
1ST-8DATA-1PAR-2SP
ST LSB MSB PAR 2SP
1ST-7DATA-1PAR-2SP
ST LSB MSB PAR 2SP
Clock synchronous Serial I/O
LSB first
Serial I/O2
Clock synchronous Serial I/O
LSB first MSB first
ST :Start bit SP :Stop bit PAR :Parity bit
Fig. 2.3.16 Setting of Serial I/O transfer data format
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2.3 Serial I/O
2.3.5 Serial I/O application examples (1) Communication using a clock synchronous serial I/O (transmit/receive) _____ Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The SRDY signal is used for communication control. Figure 2.3.17 shows a connection diagram, and Figure 2.3.18 shows a timing chart.
Transmitting side
Receiving side
P41/INT0
SRDY1
SCLK1 TXD 3802 group
SCLK RXD 3802 group
Fig. 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O] Specifications : * * * * The Serial I/O1 is used (clock synchronous serial I/O is selected) Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32) _____ The SRDY1 (receivable signal) is _____ used. The receiving side outputs the SRDY1 signal at intervals of 2 ms (generated by timer), and 2-byte data is transferred from the transmitting side to the receiving side.
SRDY1
****
SCLK1 TXD
****
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
****
2 ms
Fig. 2.3.18 Timing chart [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7 b0
SIO1STS
Transmit buffer empty flag * Check to be transferred data from the Transmit buffer register to Transmit shift register. * Writable the next transmission data to the Transmit buffer register at being set to "1." Transmit shift register shift completion flag Check a completion of transmitting 1-byte data with this flag "1" : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON
1101
00
BRG counter source selection bit : f(XIN) Serial I/O1 synchronous clock selection bit : BRG/4 Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O1 mode selection bit : Clock synchronous serial I/O Serial I/O1 enable bit : Serial I/O1 enabled
Baud rate generator (Address : 1C16)
b7 b0
BRG
7
Set "division ratio - 1"
Interrupt edge selection register (Address : 3A16)
b7 b0
INTEDGE
0
INT0 active edge selection bit : Select INT0 falling edge
Fig. 2.3.19 Setting of related registers at a transmitting side [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7 b0
SIO1STS
Receive buffer full flag Check a completion of receiving 1-byte data with this flag. "1" : At completing to receive "0" : At reading out a receive buffer
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON 1 1 1 1
11
Serial I/O1 synchronous clock selection bit : External clock
SRDY1 output enable bit : Use the SRDY1 output
Transmit enable bit : Transmit enabled Set this bit to "1," using SRDY1 output. Receive enable bit : Receive enabled Sirial I/O1 mode selection bit : Clock synchronous serial I/O Serial I/O1 enable bit : Serial I/O1 enabled
Fig. 2.3.20 Setting of related registers at a receiving side [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
Control procedure : Figure 2.3.21 shows a control procedure at a transmitting side, and Figure 2.3.22 shows a control procedure at a receiving side.
RESET
q
X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SIO1CON (Address : 1A16) 1101XX002 (Address : 1C16) 8--1 BRG 0 INTEDGE (Address : 3A16), bit0
.
IREQ1 (Address:3C16), bit0? 1 IREQ1 (Address : 3C16), bit0 0
0
* Detect INT0 falling edge
TB/RB (Address : 1816)
The first byte of a transmission data
* Write a transmission data The Transmit buffer empty flag is set to "0" by this writing.
SIO1STS (Address : 1916), bit0? 1 TB/RB (Address : 1816)
0
* Check to be transfered data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag) * Write a transmission data The transmit buffer empty flag is set to "0" by this writing.
The second byte of a transmission data
SIO1STS (Address : 1916), bit0? 1
0 * Check to be transfered data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag)
SIO1STS (Address : 1916), bit2? 1
0
* Check a shift completion of the Transmit shift register (Transmit shift register shift completion flag)
Fig. 2.3.21 Control procedure at a transmitting side [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
RESET
qX
: This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SIO1CON (Address : 1A16)
.
1111 X11X2
Pass 2 ms? Y TB/RB (Address : 1816)
N * An interval of 2 ms is generated by a timer.
Dummy data
* SRDY1 output SRDY1 signal is output by writing data to the TB/RB. Using the SRDY1 , the transmit enabled bit (bit4) of the SIO1CON is set to "1." * Check a completion of receiving (Receive buffer full flag)
SIO1STS (Address : 1916), bit1? 1 Read out reception data from TB/RB (Address : 1816)
0
* Receive the first byte data. A Receive buffer full flag is set to "0" by reading data.
0 SIO1STS (Address : 1916), bit1? 1 Read out reception data from TB/RB (Address : 1816) * Receive the second byte data. A Receive buffer full flag is set to "0" by reading data. * Check a completion of receiving (Receive buffer full flag)
Fig. 2.3.22 Control procedure at a receiving side [Communication using a clock synchronous serial I/O]
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2.3 Serial I/O
(2) Output of serial data (control of a peripheral IC) Outline : 4-byte data is transmitted and received through the clock synchronous serial I/O. The CS signal is output to a peripheral IC through the port P53.
P53 SCLK1 TXD
CS CLK DATA
CS CLK DATA
P53 SCLK2 SOUT2
CS CLK DATA
CS CLK DATA
3802 group
Peripheral IC
3802 group
Peripheral IC
(1) Example for using Serial I/O1
(2) Example for using Serial I/O2
Fig. 2.3.23 Connection diagram [Output of serial data]
Specifications : * * * * *
The Serial I/O is used. (clock synchronous serial I/O is selected) Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32) Transfer direction : LSB first The Serial I/O interrupt is not used. ___ The Port P53 is connected to the CS pin ("L" active) of the peripheral IC for a transmission control (the output level of the port P53 is controlled by software).
Figre 2.3.24 shows an output timing chart of serial data.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Note: The SOUT2 pin is in high impedance after completing to transfer data, using the serial I/O2
Fig. 2.3.24 Timing chart [Output of serial data]
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2.3 Serial I/O
Figure 2.3.25 shows a setting of serial I/O1 related registers, and Figure 2.3.26 shows a setting of serial I/O1 transmission data.
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON
11011000
BRG count source selection bit : f(XIN) Serial I/O1 synchronous clock selection bit : BRG/4 SRDY1 output enable bit : Not use the SRDY1 signal output function Transmit interrupt source selection bit : Transmit shift operating completion Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O1 mode selection bit : Clock synchronous serial I/O Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7 b0
UARTCON
0
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C16)
b7 b0
BRG
b7
7
Set "division ratio - 1"
Interrupt control register 1 (Address : 3E16)
b0
ICON1
0
Serial I/O1 transmit interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C16)
b7 b0
IREQ1
0
Serial I/O1 transmit interrupt request bit Using this bit, check the completion of transmitting 1-byte base data. "1" : Transmit shift completion
Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data]
Transmit/Receive buffer register (Address : 1816)
b7 b0
TB/RB
Set a transmission data. Check that transmission of the previous data is completed before writing data (bit 3 of the Interrupt request register 1 is set to "1").
Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data]
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2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.25, the Serial I/O1 can transmit 1-byte data simply by writing data to the Transmit buffer register. Thus, after setting the CS signal to "L," write the transmission data to the Receive buffer register on a 1-byte base, and return the CS signal to "H" when the desired number of bytes have been transmitted. Figure 2.3.27 shows a control procedure of serial I/O1.
RESET
qX
: This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SIO1CON (Address : 1A16) 110110002 0 UARTCON (Address : 1B16), bit4 (Address : 1C16) 8-1 BRG (Address : 3E16), bit3 0 ICON1 (Address : 0A16), bit3 1 P5 (Address : 0B16) XXXX1XXX2 P5D
.
q
Set the Serial I/O1. Serial I/O1 transmit interrupt : Disabled Set the CS signal output port. ("H" level output)
q
q
.
P5 (Address : 0A16), bit3
0
q
Set the CS signal output level to "L."
IREQ1 (Address : 3C16), bit3
0
q
Set the Serial I/O1 transmit interrupt request bit to "0."
TB/RB (Address : 1816)
a transmission data
q
Write a transmission data. (start to transmit 1-byte data)
IREQ1 (Address : 3C16), bit3? 1
0
q
Check the completion of transmitting 1byte data.
N
Complete to transmit data? Y
q
q
Use any of RAM area as a counter for counting the number of transmitted bytes. Check that transmission of the target number of bytes has been completed. Return the CS signal output level to "H" when transmission of the target number of bytes is completed.
P5 (Address : 0A16), bit3
1
q
Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data]
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2.3 Serial I/O
Figure 2.3.28 shows a setting of serial I/O2 related registers, and Figure 2.3.29 shows a setting of serial I/O2 transmission data.
Serial I/O2 control register (Address : 1D16)
b7 b0
SIO2CON
01001010
Internal synchronous clock selection bits : f(XIN)/32 Serial I/O2 port selection bit : Use the Serial I/O2 SRDY2 output enable bit : Not use the SRDY2 signal output function Transfer direction selection bit : LSB first Serial I/O2 synchronous clock selection bit : Internal clock P51/SOUT2 P-channel output disable bit : CMOS output
Interrupt control register 2 (Address : 3F16)
b7 b0
ICON2
0
Serial I/O2 interrupt enable bit : Interrupt disabled
Interrupt request register 2 (Address : 3D16)
b7 b0
IREQ2
0
Serial I/O2 interrupt request bit Using this bit, check the completion of transmitting 1-byte base data. "1" : Transmit completion
Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data]
Serial I/O2 register (Address : 1F16)
b7 b0 Set a transmission data. Check that transmission of the previous data is completed before writing data (bit 2 of the Interrupt request register 2 is set to "1").
SIO2
Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data]
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2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.28, the Serial I/O2 can transmit 1-byte data simply by writing data to the Serial I/O2 register. Thus, after setting the CS signal to "L," write the transmission data to the Serial I/O1 register on a 1-byte base, and return the CS signal to "H" when the desired number of bytes have been transmitted. Figure 2.3.30 shows a control procedure of serial I/O2.
RESET
q
X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization 010010102 SIO2CON(Address : 1D16) 0 ICON2 (Address : 3F16), bit2 1 (Address : 0A16), bit3 P5 XXXX1XXX2 (Address : 0B16) P5D
.
q q q
Set the Serial I/O2 control register. Serial I/O2 interrupt : Disabled Set the CS signal output port. ("H" level output)
.
P5 (Address : 0A16), bit3 0
q
Set the CS signal output level to "L."
IREQ2 (Address : 3D16), bit2
0
q
Set the Serial I/O2 interrupt request bit to "0."
SIO2 (Address : 1F16)
a transmission data
q
Write a transmission data. (start to transmit 1-byte data)
IREQ2 (Address : 3D16), bit2? 1 N
0
q
Check the completion of transmitting 1byte data.
Complete to transmit data? Y
q
q
Use any of RAM area as a counter for counting the number of transmitted bytes. Check that transmission of the target number of bytes has been completed. Return the CS signal output level to "H" when transmission of the target number of bytes is completed.
P5 (Address : 0A16), bit3
1
q
Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data]
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2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of a specified number of bytes) between microcomputers [without using an automatic transfer] Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock and the data between the transmitting and receiving sides may be lost because of noise included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This "heading adjustment" is carried out by using the interval between blocks in this example.
SCLK RXD TXD Master unit
SCLK TXD RXD Slave unit
Note: Use SOUT and SIN instead of TXD and RXD in the serial I/O2.
Fig. 2.3.31 Connection diagram [Cyclic transmission or reception of block data between microcomputers]
Specifications : * * * * * * * *
The serial I/O1 is used (clock synchronous serial I/O is selected). Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32) Byte cycle: 488  s Number of bytes for transmission or reception : 8 byte/block Block transfer cycle : 16 ms Block transfer period : 3.5 ms Interval between blocks : 12.5 ms Heading adjustive time : 8 ms
Limitations of the specifications 1. Reading of the reception data and setting of the next transmission data must be completed within the time obtained from "byte cycle - time for transferring 1-byte data" (in this example, the time taken from generating of the Serial I/O1 receive interrupt request to generating of the next synchronizing clock is 431  s). 2. "Heading adjustive time < interval between blocks" must be satisfied.
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2.3 Serial I/O
The communication is performed according to the timing shown below. In the slave unit, when a synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is processed as the beginning (heading) of a block. When a clock is input again after one block (8 byte) is received, the clock is ignored. Figure 2.3.33 shows a setting of related registers.
D0
D1
D2
D7
D0
Byte cycle Block transfer period Block transfer cycle Heading adjustive time Interval between blocks
Processing for heading adjustment
Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers]
Master unit
Serial I/O1 control register (Address : 1A16) b7 b0 SIO1CON 1 1 1 1 1 0 0 0 BRG count source : f(XIN) Synchronous clock : BRG/4 Not use the SRDY1 output Transmit interrupt source : Transmit shift operating completion Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O1 enabled
Slave unit
Serial I/O1 control register (Address : 1A16) b7 b0 SIO1CON 1 1 1 1
01
Not be effected by external clock Synchronous clock : External clock Not use the SRDY1 output Not use the serial I/O1 transmit interrupt Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O1 enabled
Both of units
UART control register (Address : 1B16) b7 b0 UARTCON
0
P45/TXD pin : CMOS output Baud rate generator (Address : 1C16) b7 b0
BRG
7
Set "division ratio - 1"
Fig. 2.3.33 Setting of related registers [Cyclic transmission or reception of block data between microcomputers]
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APPLICATION
2.3 Serial I/O
Control procedure :  Control in the master unit After a setting of the related registers is completed as shown in Figure 2.3.33, in the master unit transmission or reception of 1-byte data is started simply by writing transmission data to the Transmit buffer register. To perform the communication in the timing shown in Figure 2.3.32, therefore, take the timing into account and write transmission data. Read out the reception data when the Serial I/O1 transmit interrupt request bit is set to "1," or before the next transmission data is written to the Transmit buffer register. A processing example in the master unit using timer interrupts is shown below.
Interrupt processing routine executed every 488  s
CLT (Note 1) CLD (Note 2) Push register to stack
q
Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack.
Within a block transfer period? Y Read a reception data
N
q
Generate a certain block interval by using a timer or other functions.
q
Count a block interval counter
Check the block interval counter and determine to start of a block transfer.
Complete to transfer a block? N Write a transmission data
Y
Start a block transfer? Y Write the first transmission data (first byte) in a block
N
Pop registers
q
Pop registers which is pushed to stack.
RTI
Fig. 2.3.34 Control in the master unit
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2.3 Serial I/O
 Control in the slave unit After a setting of the related registers is completed as shown in Figure 2.3.33, the slave unit becomes the state which is received a synchronizing clock at all times, and the Serial I/O1 receive interrupt request bit is set to "1" every time an 8-bit synchronous clock is received. By the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to the Transmit buffer register after received data is read out. However, if no serial I/O1 receive interrupt occurs for more than a certain time (head adjustive time), the following processing will be performed. 1. The first 1 byte data of the transmission data in the block is written into the Transmit buffer register. 2. The data to be received next is processed as the first 1 byte of the received data in the block. Figure 2.3.35 shows the control in the slave unit using a serial I/O1 receive interrupt and any timer interrupt (for head adjustive).
Serial I/O1 receive interrupt processing routine
Timer interrupt processing routine
CLT (Note 1) CLD (Note 2) Push register to stack
q
Push the register used in the interrupt processing routine into the stack. Check the received byte counter to judge if a block has been transfered.
CLT (Note 1) CLD (Note 2) Push register to stack
q
Push the register used in the interrupt processing routine into the stack.
q
Within a block transfer period? Y Read a reception data
N
Heading adjustive counter - 1
Heading adjustive counter = 0? Y
N
A received byte counter +1
Write the first transmission data (first byte) in a block
A received byte counter  8? N
Y
A received byte counter
0
Pop registers Write a transmission data Write any data (FF16) RTI Heading adjustive counter Initialized value (Note 3)
q
Pop registers which is pushed to stack.
Pop registers
q
Pop registers which is pushed to stack. Notes 1: When using the Index X mode flag (T). 2: When using the Decimal mode flag (D). 3: In this example, set the value which is equal to the heading adjustive time divided by the timer interrupt cycle as the initialized value of the heading adjustive counter. For example: When the heading adjustive time is 8 ms and the timer interrupt cycle is 1 ms, set 8 as the initialized value.
RTI
Fig. 2.3.35 Control in the slave unit
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APPLICATION
2.3 Serial I/O
(4) Communication (transmit/receive) using an asynchronous serial I/O (UART) Point : 2-byte data is transmitted and received through an asynchronous serial I/O. The port P40 is used for communication control. Figure 2.3.36 shows a connection diagram, and Figure 2.3.37 shows a timing chart.
Transmitting side
P40
Receiving side
P40
TXD
RXD
3802 group
3802 group
Fig. 2.3.36 Connection diagram [Communication using UART]
Specifications : * The Serial I/O1 is used (UART is selected). * Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz is divided by 512) * Communication control using port P40 (The output level of the port P40 is controlled by softoware.) * 2-byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms (generated by timer).
P40
TXD
ST D0
D1 D2 D3 D4 D5 D6
D7 SP(2) ST D0 D1 D2 D3
D4 D5 D6 D7 SP(2)
ST D0
10 ms
Fig. 2.3.37 Timing chart [Communication using UART]
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APPLICATION
2.3 Serial I/O
Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values, Figure 2.3.38 shows a setting of related registers at a transmitting side, and Figure 2.3.39 shows a setting of related registers at a receiving side. Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values Transfer bit BRG count at f(XIN) = 4.9152 MHZ at f(XIN) = 7.3728 MHZ at f(XIN) = 8 MHZ rate (bps) source (Note 1) (Note 2) BRG setting value Actual time (bps) BRG setting value Actual time (bps) BRG setting value Actual time (bps) 600 1200 2400 4800 9600 19200 38400 76800 31250 62500 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN) f(XIN) f(XIN) 127(7F16) 63(3F16) 31(1F16) 15(0F16) 7(0716) 3(0316) 1(0116) 3(0316) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 191(BF16) 95(5F16) 47(2F16) 23(1716) 11(0B16) 5(0516) 2(0216) 5(0516) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 207(CF16) 103(6716) 51(3316) 25(1916) 12(0C16) 5(0516) 2(0216) 5(0516) 15(0F16) 7(0716) 600.96 1201.92 2403.85 4807.69 9615.38 20833.33 41666.67 83333.33 31250.00 62500.00
Notes 1: Equation of transfer bit rate Transfer bit rate (bps) = f(XIN) (BRG setting value + 1) ! 16 ! m
m: when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to "0," a value of m is 1. when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to "1," a value of m is 4. 2: A BRG count source is selected by bit 0 of the Serial I/O1 control register (Address : 1A16).
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2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916)
b7 b0
SIO1STS
Transmit buffer empty flag * Check to be transferred data from the Transmit buffer register to the Transmit shift register. * Writable the next transmission data to the Transmit buffer register at being set to "1." Transmit shift register shift completion flag Check a completion of transmitting 1-byte data with this flag. "1" : Transmit shift completed
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON 1 0 0 1
001
BRG count source selection bit : f(XIN)/4 Serial I/O1 synchronous clock selection bit : BRG/16
SRDY1 output enable bit : Not use SRDY1 out
Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O1 mode selection bit : Asynchronous serial I/O(UART) Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7 b0
UARTCON
01
00
Character length selection bit : 8 bits Parity enable bit : Parity checking disabled Stop bit length selection bit : 2 stop bits P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C16)
b7 b0
BRG
7
Set
f(XIN) Transfer bit rate
16
mT
-1
T when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to "0," a value of m is 1. when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to "1," a value of m is 4.
Fig. 2.3.38 Setting of related registers at a transmitting side [Communication using UART]
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APPLICATION
2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916)
b7 b0
SIO1STS
Receive buffer full flag Check a completion of receiving 1-byte data with this flag. "1" : at completing to receive "0" : at reading out a content of the Receive buffer register Overrun error flag "1" : when data are ready to be transferred to the Receive shift register in the state of storing data into the Receive buffer register.
Parity error flag "1" : when parity error occurs at enabled parity. Framing error flag "1" : when data can not be received at the timing of setting a stop bit. Summing error flag "1" : when even one of the following errors occurs. * Overrun error * Parity error * Framing error
Serial I/O1 control register (Address : 1A16)
b7 b0
SIO1CON
1010
001
BRG count source selection bit : f(XIN)/4 Serial I/O1 synchronous clock selection bit : BRG/16
SRDY1 output enable bit : Not use SRDY1 out
Transmit enable bit : Transmit disabled Receive enable bit : Receive enabled Serial I/O1 mode selection bit : Asynchronous serial I/O(UART) Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B16)
b7 b0
UARTCON
1
00
Character length selection bit : 8 bits Parity enable bit : Parity checking disabled Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 1C16)
b7 b0
BRG
7
Set
f(XIN) Transfer bit rate 16
mT
-1
T when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to "0," a value of m is 1. when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to "1," a value of m is 4.
Fig. 2.3.39 Setting of related registers at a receiving side [Communication using UART] 2-50
3802 GROUP USER'S MANUAL
APPLICATION
2.3 Serial I/O
Control procedure : Figure 2.3.40 shows a control procedure at a transmitting side, and Figure 2.3.41 shows a control procedure at a receiving side.
RESET
qX
: This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization 1001X0012 SIO1CON (Address : 1A16) 000010002 UARTCON (Address : 1B16) (Address : 1C16) 8 -1 BRG 0 (Address : 0816), bit0 P4 (Address : 0916) XXXXXXX12 P4D
.
* Set port P40 for a communication control.
Pass 10 ms? Y P4 (Address : 0816), bit0 1
N
* An interval of 10 ms is generated by a timer.
* Start of communication. * Write a transmission data The Transmit buffer empty flag is set to "0" by this writing. * Check to be transferred data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag)
TB/RB (Address : 1816)
The first byte of a transmission data
SIO1STS (Address : 1916), bit0? 1 The second byte of a transmission data
0
TB/RB (Address : 1816)
* Write a transmission data The Transmit buffer empty flag is set to "0" by this writing.
SIO1STS (Address : 1916), bit0? 1
0
* Check to be transferred data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag)
SIO1STS (Address : 1916), bit2?
1
0
* Check a shift completion of the Transmit shift register. (Transmit shift register shift completion flag)
P4 (Address : 0816), bit0
0
* End of communication
Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART]
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APPLICATION
2.3 Serial I/O
RESET
q
X :This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.
Initialization SIO1CON UARTCON BRG P4D
.
(Address : 1A16) (Address : 1B16) (Address : 1C16) (Address : 0916)
1010X0012 000010002 8-1 XXXXXXX02
SIO1STS (Address : 1916), bit1?
1
0
* Check a completion of receiving. (Receive buffer full flag) * Receive the first 1 byte data A Receive buffer full flag is set to "0" by reading data.
Read out a reception data from RB (Address : 1816)
SIO1STS (Address : 1916), bit6? 0
1
* Check an error flag.
SIO1STS (Address : 1916), bit1?
1
0
* Check a completion of receiving. (Receive buffer full flag)
Read out a reception data from RB (Address : 1816)
* Receive the second byte data A Receive buffer full flag is set to "0" by reading data. 1 * Check an error flag. Processing for error
SIO1STS (Address : 1916), bit6? 0
1
P4 (Address : 0816), bit0?
0
SIO1CON (Address : 1A16) SIO1CON (Address : 1A16)
0000X0012 1010X0012
* Countermeasure for a bit slippage
Fig. 2.3.41 Control procedure at a receiving side [Communication using UART]
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2.4 PWM
2.4 PWM
2.4.1 Memory map of PWM
002B16 002C16 002D16
PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM)
Fig. 2.4.1 Memory map of PWM related registers
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APPLICATION
2.4 PWM
2.4.2 Related registers
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0 PWM control register (PWMCON) [Address:2B16]
B
Name
Function
0 : PWM disabled 1 : PWM enabled 0 : f(XIN) 1 : f(XIN)/2
At reset
RW
0 PWM function enable bit 1 Count source selection bit
0 0 0 0 0 0 0 0
! ! ! ! ! !
2 Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are "0".
3 4 5 6 7 Fig. 2.4.2 Structure of PWM control register
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0 PWM prescaler (PREPWM) [Address : 2C16]
B 0 1 2 3 4 5 6 7
q PWM
Function
cycle is set. q The values set in this register is written to both the PWM prescaler pre-latch and the PWM prescaler latch at the same time. q When data is written during outputting PWM, the pulses corresponding to the changed contents are output starting with the next cycle. q When this register is read out, the content of the PWM prescaler latch is read out.
At reset
RW
? ? ? ? ? ? ? ?
Fig. 2.4.3 Structure of PWM prescaler
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2.4 PWM
PWM register
b7 b6 b5 b4 b3 b2 b1 b0 PWM register (PWM) [Address : 2D16]
b 0 1 2
Function
q q q
At reset
RW
q
3 4 5 6 7
"H" level output period of PWM is set. The values set in this register is written both the PWM register pre-latch and the PWM register latch at the same time. When data is written during outputting PWM, the pulses corresponding to the changed contents are output starting with the next cycle. When this register is read out, the content of the PWM register latch is read out.
? ? ? ? ? ? ? ?
Fig. 2.4.4 Structure of PWM register
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APPLICATION
2.4 PWM
2.4.3 PWM output circuit application example (1) Control of motor Outline : The rotation speed of the motor is controlled by using PWM (pulse width modulation) output. Figure 2.4.5 shows a connection diagram, Figures 2.4.6 shows PWM output timing, and Figure 2.4.7 shows a setting of the related registers.
P56/PWM D-A converter
M Motor driver
3802 group
Fig. 2.4.5 Connection diagram Specifications : * Motor is controlled by using the 8-bit-resolution PWM output function. * Clock f(XIN) = 5.0 MHz * "T," PWM cycle : 102  s * "t," "H" level width of output pulse : 40  s (Fixed speed)V V A motor speed can be changed by changing the "H" level width of output pluse.
t = 40  s
PWM output T = 102  s
Fig. 2.4.6 PWM output timing
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APPLICATION
2.4 PWM
PWM control register (Address : 2B16)
b7 b0
PWMCON
01
PWM function enable bit : PWM enabled (Note) Count source selection bit : f(XIN) Note : The PWM output function is given priority even when the corresponding bit to P56 pin of Port P5 direction register is set to "0" (input mode).
PWM prescaler (Address : 2C16)
b7 b0
PREPWM
n
Set "T", PWM cycle n=1
[Equation] 255 ! (n + 1) T= f(XIN)
PWM register (Address : 2D16)
b7 b0
PWM
m
Set "t", "H" level width of PWM m = 100
[Equation] T!m t= 255
Fig. 2.4.7 Setting of related registers [About PWM output] 1. Set the PWM function enable bit to "1" : The P56/PWM pin is used as the PWM pin. "H" level pulse is output first. 2. Set the PWM function enable bit to "0" : The P56/PWM pin is used as the port P56. Thus, when fixing the output level, make sure the following. * First, write an output value to bit 6 of the Port P5 register. * Then write "X1XXXXXX2" to the Port P5 direction register. (X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded.) 3. After data is set to the PWM prescaler and the PWM register, the PWM waveforms corresponding to new data will be output from the next repetitive cycle.
PWM output
Change PWM output data
From the next repetitive cycle, output modified data
Fig. 2.4.8 PWM output
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APPLICATION
2.4 PWM
Control procedure : By setting the related registers as shown to Figure 2.4.7, PWM waveforms are output to the externalunit. This PWM output is integrated through the low pass filter and converted into DC signals for control of the motor. Figure 2.4.9 shows control procedure.
~ ~
P5 (Address : 0A16), bit6 P5D (Address : 0B16) 0 X1XXXXXX2 1 100 000000012 PREPWM (Address : 2C16) PWM (Address : 2D16) PWMCON (Address : 2B16)
* X : This bit is not used in this application. Set it to "0" or "1." It's value can be disregarded. * Output "L" level from P56/PWM pin.
* Set the PWM cycle * Set the "H" level width of PWM * Select the PWM count source, and enable the PWM output.
~ ~
Fig. 2.4.9 Control procedure
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2.5 A-D converter
2.5 A-D converter
2.5.1 Memory map of A-D conversion
003416 003516 003D16 003F16
AD/DA control register (ADCON) A-D conver sion register (AD) Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2)
Fig. 2.5.1 Memory map of A-D conversion related registers
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APPLICATION
2.5 A-D converter
2.5.2 Related registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0 AD/DA control register (ADCON) [Address : 3416]
B
Name
b2 b1 b0
Function
At reset
RW
0 Analog input pin selection bits 0 0 0 : P60/AN0 0 0 1 : P61/AN1 0 1 0 : P62/AN2 1 0 1 1 : P63/AN3 1 0 0 : P64/AN4 1 0 1 : P65/AN5 2 1 1 0 : P66/AN6 1 1 1 : P67/AN7 AD conversion completion bit 0 : Conversion in progress 3 1 : Conversion completed 4 Nothing is allocated for these bits. These are write disabled bits. 5 When these bits are read out, the values are "0." 0 : DA1 output disable 6 DA1 output enable bit 1 : DA1 output enable 7 DA2 output enable bit
0 : DA2 output disabled 1 : DA2 output enabled
0 0 0 1 0 0 0 0
! !
Fig. 2.5.2 Structure of AD/DA control register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address : 3516]
B Function 0 The read-only register which A-D conversion results are stored. 1 2 3 4 5 6 7
At reset
RW
! ! ! ! ! ! ! !
? ? ? ? ? ? ? ?
Fig. 2.5.3 Structure of A-D conversion register
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2.5 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address : 3D16]
B Name 0 CNTR0 interrupt request bit 1 CNTR1 interrupt request
bit 2 Serial I/O2 interrupt request bit 3 INT2 interrupt request bit
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T !
0 0 0 0 0 0 0 0
4 INT3 interrupt request bit 5 INT4 interrupt request bit
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 6 AD conversion interrupt request bit 1 : Interrupt request Nothing is allocated for this bit. This is a write disabled bit. 7 When this bit is read out, the value is "0." T "0" is set by software, but not "1."
Fig. 2.5.4 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name B CNTR0 interrupt enable bit 0 1 CNTR1 interrupt enable bit 2 Serial I/O2 interrupt enable
bit
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 0 0 0 0 0 0 0
3 INT2 interrupt enable bit 4 INT3 interrupt enable bit 5 INT4 interrupt enable bit 6 AD conversion interrupt
enable bit
7 Fix this bit to "0."
Fig. 2.5.5 Structure of Interrupt control register 2
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2.5 A-D converter
2.5.3 A-D conversion application example Conversion of Analog input voltage Outline : The analog input voltage input from the sensor is converted into digital values. Figure 2.5.6 shows a connection diagram, and Figure 2.5.7 shows a setting of related registers.
P60/AN0
Sensor
3802 group
Fig. 2.5.6 Connection diagram [Conversion of Analog input voltage]
Specifications : * The analog input voltage input from the sensor is converted into digital values. * The P60/AN0 pin is used as an analog input pin.
AD/DA control register (Address : 3416)
b7 b0
ADCON
0000
Analog input pin selection bits : Select the P60/AN0 pin AD conversion completion bit : Conversion in progress
A-D conversion register (Address : 3516)
b7 b0 (read-only) Store a result of A-D conversion (Note)
AD
Note: Read out a result of A-D conversion after bit 3 of the AD/DA control register (ADCON) is set to "1."
Fig. 2.5.7 Setting of related registers [Conversion of Analog input voltage]
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APPLICATION
2.5 A-D converter
Control procedure : By setting the related registers as shown in Figure 2.5.7, the analog input voltage input from the sensor are converted into digital values.
~ ~
ADCON (Address : 3416), bit0 - bit2 ADCON (Address : 3416), bit3 0002 0
* Select the P60/AN0 pin as an analog input pin. * Start A-D conversion.
ADCON (Address : 3416), bit3? 1 Read out AD (Address : 3516)
0
* Check the completion of A-D conversion.
* Read out the conversion result.
~ ~
Fig. 2.5.8 Control procedure [Conversion of Analog input voltage]
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APPLICATION
2.6 Processor mode
2.6 Processor mode
2.6.1 Memory map of processor mode
003B16
CPU mode register (CPUM )
Fig. 2.6.1 Memory map of processor mode related register
2.6.2 Related register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Adress : 3B16]
B Name 0 Processor mode bits 1 2 Stack page selection bit
Function
00 : Single-chip mode 01 : Memory expansion mode 10 : Microprocessor mode 11 : Not available 0 : 0 page 1 : 1 page
At reset
RW
0
T
0 0 0 0 0 0
! ! ! ! !
3 Nothing is allocated for these bits. These are write disabled bits. 4 When these bits are read out, the values are "0." 5 6 7
T An initial value of bit 1 is determined by a level of the CNVSS pin.
Fig. 2.6.2 Structure of CPU mode register
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2.6 Processor mode
2.6.3 Processor mode application examples ____ (1) Application example of memory expansion in the case where the ONW (One-Wait) function is not used Outline : The external memory is accessed in the microprocessor mode. At f(XIN) = 8 MHz, an available RAM is given by the following : ___ * OE access time : ta (OE)  50 ns * Setup time for writing data : tsu (D)  65 ns For example, the M5M5256BP-10 whose address access is 100 ns is available. Figure 2.6.3 shows an expansion example of a 32K byte ROM and a 32K byte RAM.
3802 group CNVSS AD15 ONW 2 P30, P31 AD14 AD0 8 P4 DB0 DB7 8 P5
-
8
M5M27C256AK-10 CE 74F04
15
M5M5256BP-10 S
RD 8 P6 WR
Fig. 2.6.3 Expansion example of ROM and RAM
-
A0-A14 EPROM
A0-A14 SRAM
D0-D7 OE
DQ1-DQ8 Memory map OE W 000016 000816 External RAM area
(M5M5256BP)
SFR area 004016 Internal RAM area 044016 External RAM area
(M5M5256BP )
8MHz
VCC = 5.0V  10 %
800016 FFFF16
External ROM area
(M5M27C256AK )
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APPLICATION
2.6 Processor mode
Figure 2.6.4, Figure 2.6.5 and Figure 2.6.6 show a standard timing at 8 MHz (No-Wait).
A0-A7
(Port P0)
Address (low-order)
A8-A14
(Port P1)
Address (high-order)
S
(A15)
OE
(RD of 3802)
td(AH - RD)
125 ns - 35 ns (min)
ta(OE)
50 ns (max)
DQ1-DQ8
(Port P2)
,,,,,,, ,,,,,,,
125 ns - 10 ns (min)
tWL(RD)
Data
tsu(DB - RD)
65 ns (min)
WR
" H " level
td(AH - RD) tWL(RD) ta(OE) tsu(DB - RD)
: RD delay time after outputting address of 3802 : RD pulse width of 3802 : Output enabled access time of M5M5256BP : Data bus setup time before RD of 3802
Fig. 2.6.4 Read-cycle (OE access, SRAM)
A0-A7
(Port P0)
Address (low-order)
A8-A14
(Port P1)
Address (high-order)
CE
5.8 ns (max)
tPHL
OE
(RD of 3802)
td(AH - RD)
125 ns - 35 ns (min)
tWL(RD) ta(OE)
50 ns (max)
D0-D7
(Port P2)
WR
,,,,,,, ,,,,,,,
125 ns - 10ns (min)
Data
tsu(DB - RD)
65 ns (min)
" H " level
tPHL td(AH - RD) tWL(RD) ta(OE) tsu(DB - RD)
: : : : :
Output delay time of 74F04 RD delay time after outputting address of 3802 RD pulse width of 3802 Output enabled access time of M5M27C256AK Data bus setup time before RD of 3802
Fig. 2.6.5 Read-cycle (OE access, EPROM)
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3802 GROUP USER'S MANUAL
APPLICATION
2.6 Processor mode
A0-A7
(Port P0)
Address (low-order)
A8-A14
(Port P1)
Address (high-order)
S
(A15)
W
(WR of 3802)
td(AH - WR)
125 ns - 35 ns (min)
tWL(WR)
125 ns - 10 ns (min)
td(WR - DB) DQ1-DQ8
(Port P2) 65 ns (max)
,,,,,,, ,,,,,,,
Data tsu(D)
35 ns (min)
OE
(RD of 3802)
" H " level
td(AH - WR) tWL(WR) td(WR - DB) tsu(D)
: WR delay time after outputting address of 3802 : WR pulse width of 3802 : Data bus delay time after WR of 3802 : Data setup time of M5M5256BP
Fig. 2.6.6 Write-cycle (W control, SRAM)
3802 GROUP USER'S MANUAL
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APPLICATION
2.6 Processor mode
_____
(2) Application example of memory expansion in the case where the ONW (One-Wait) function is used ____ Outline : ONW function is used when the external memory access is slow. ____ If "L" level signal is input to the P32/ONW pin while the CPU is in the read or write status, the read or write cycle corresponding to 1 cycle of is extended. In the extended period, ___ ___ ____ the RD or WR signal is kept at the "L" level. The ONW function operates only when data is read from or written into addresses 0000 16 to 000716 and addresses 044016 to FFFF16 . ____ Figure 2.6.7 shows an application example of the ONW function.
3802 group CNVSS
AD15 74F04 M5M27C 256A K-10 CE
2
P30, P31 ONW AD14
M5M5256B P-10 S A0-A14 SRAM
8
P4
15
A0-A14 EPRO M
AD0
DB0
-
-
8
8
P5
D0-D7 OE
DQ1-DQ8 OE W
DB7
Memory map 000016 External RAM area
(M5M5256B P )
000816 8 P6 RD WR
SFR area 004016 Internal RAM area 044016 External RAM area
(M5M5256B P )
8MH z
VCC = 5.0V10 %
800016 External ROM area FFFF16
(M5M27C256A K )
Fig. 2.6.7 Application example of the ONW function
____
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3802 GROUP USER'S MANUAL
APPLICATION
2.7 Reset
2.7 Reset
2.7.1 Connection example of reset IC
91 1
VCC
Power source
M62022L
GND
3
5
Output
35
RESET
Delay capacity
4
0.1  F
40
VSS
3802 group
Fig. 2.7.1 Example of Poweron reset circuit
Figure 2.7.2 shows the system example which switch to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt.
System power source voltage +5
91 + 7
VCC
VCC1 RESET
2
5
35
RESET
VCC2
INT
3 40
INT VSS
1
V1 GND Cd
4
6
3802 group
M62009L, M62009P, M62009FP
Fig. 2.7.2 RAM back-up system
3802 GROUP USER'S MANUAL
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CHAPTER 3 APPENDIX
3.1 Electrical characteristics 3.2 Standard characteristics 3.3 Notes on use 3.4 Countermeasures against noise 3.5 List of registers 3.6 Mask ROM ordering method 3.7 Mark specification form 3.8 Package outline 3.9 List of instruction codes 3.10 Machine instructions 3.11 SFR memory map 3.12 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1Electrical characteristics
3.1.1 ABSOLUTE MAXIMUM RATINGS
Table 3.1.1 Absolute maximum ratings Symbol Parameter VCC Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, VI P60-P67, VREF VI Input voltage RESET, XIN VI Input voltage CNVSS Output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, VO P60-P67, XOUT Pd Power dissipation Topr Operating temperature Tstg Storage temperature Note: 300 mW in case of the flat package. Conditions Ratings -0.3 to 7.0 -0.3 to VCC +0.3 All voltages are based on VSS. Output transistors are cut off. -0.3 to VCC +0.3 -0.3 to 13 -0.3 to VCC +0.3 Ta = 25 C 1000 (Note) -20 to 85 -40 to 125 Unit V V V V V mW C C
3.1.2 Recommended operating conditions
Table 3.1.2 RECOMMENDED OPERATING CONDITIONS (Vcc = 3.0 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Limits Symbol Parameter Min. Typ. Max. Power source voltage (f(XIN) < 2 MHz) (Note 1) 3.0 5.0 5.5 VCC Power source voltage (f(XIN) = 8 MHz) (Note 1) 4.0 5.0 5.5 VSS Power source voltage 0 Analog reference voltage (when A-D converter is used) 2.0 VCC VREF Analog reference voltage (when D-A converter is used) 3.0 VCC AVSS Analog power source voltage 0 VIA Analog input voltage AN0-AN7 AVSS VCC "H" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VIH 0.8 VCC VCC P50-P57, P60-P67 VIH "H" input voltage RESET, XIN, CNVSS 0.8 VCC VCC "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, VIL 0 0.2 VCC P50-P57, P60-P67 VIL "L" input voltage RESET, CNVSS 0.2 VCC 0 VIL "L" input voltage XIN 0.16 VCC 0 IOH(peak) "H" total peak output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 2) -80 IOH(peak) "H" total peak output current P40-P47,P50-P57, P60-P67 (Note 2) -80 IOL(peak) "L" total peak output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 2) 80 IOL(peak) "L" total peak output current P40-P47,P50-P57, P60-P67 (Note 2) 80 IOH(avg) "H" total average output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 2) -40 IOH(avg) "H" total average output current P40-P47,P50-P57, P60-P67 (Note 2) -40 IOL(avg) "L" total average output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 2) 40 IOL(avg) "L" total average output current P40-P47,P50-P57, P60-P67 (Note 2) 40 "H" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH(peak) -10 P50-P57, P60-P67 (Note 3) "L" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOL(peak) 10 P50-P57, P60-P67 (Note 3) "H" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH(avg) -5 P50-P57, P60-P67 (Note 4) "L" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOL(avg) 5 P50-P57, P60-P67 (Note 4) Internal clock oscillation frequency (VCC = 4.0 to 5.5 V) 8 f(XIN) Internal clock oscillation frequency (VCC = 3.0 to 4.0 V) 6 VCC-16 Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms. Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz
3-2
3802 GROUP USER'S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.3 ELECTRICAL CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 (Note 1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,P50-P57, P60-P67 Hysteresis Hysteresis Hysteresis "H" input current CNTR0, CNTR1, INT0-INT4 RXD, SCLK1, SIN2, SCLK2 RESET P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 RESET, CNVSS XIN P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, RESET, CNVSS RESET, CNVSS XIN Test conditions IOH = -10 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 3.0 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 3.0 to 5.5 V Min. VCC-2.0 V VCC-1.0 2.0 V 1.0 0.4 0.5 0.5 VI = VCC VI = VCC VI = VCC VI = VSS 5.0 5.0 4 -5.0 V V V A A A A Limits Typ. Max. Unit
VOH
VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH IIL IIL IIL VRAM
"H" input current "H" input current "L" input current
-5.0 A VI = VSS -4 A VI = VSS 5.5 2.0 V When clock stopped 13 6.4 f(XIN) = 8 MHz, VCC = 5 V 8 4 f(XIN) = 5 MHz, VCC = 5 V 2.0 0.8 f(XIN) = 2 MHz, VCC = 3 V When WIT instruction is executed with 1.5 mA f(Xin) = 8MHz,VCC=5V When WIT instruction is executed with 1 ICC Power source current f(Xin) = 5MHz,VCC=5V When WIT instruction is executed with 0.2 f(Xin) = 2MHz,VCC=3V When STP instruction Ta = 25 C 1 0.1 is executed with clock (Note 2) A stopped, output Ta = 85 C 10 transistors isolated. (Note 2) Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is "0". 2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin. "L" input current "L" input current RAM hold voltage
3.1.4 A-D converter characteristics
Table 3.1.4 A-D CONVERTER CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = -20 to 85 C, unless otherwise noted) Symbol -- -- tCONV RLADDER IVREF II(AD) Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current Test conditions Min. Limits Typ. 1 35 150 0.5 Max. 8 2.5 50 200 5.0 Unit Bits LSB tC() k A A
VREF = 5.0 V
50
Note: When D-A conversion registers (addresses 003616 and 003716) contain "0016".
3802 GROUP USER'S MANUAL
3-3
APPENDIX
3.1 Electrical characteristics
3.1.5 D-A CONVERTER CHARACTERISTICS
Table 3.1.5 D-A CONVERTER CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. -- Resolution 8 Bits VCC = 4.0 to 5.5 V 1.0 -- Absolute accuracy % VCC = 3.0 to 4.0 V 2.5 Setting time 3 s tsu RO Output resistor 1 2.5 4 k IVREF Reference power source input current (Note) 3.2 mA Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016", and excluding currents flowing through the A-D resistance ladder.
3-4
3802 GROUP USER'S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.6 Timing requirements and Switching characteristics
Table 3.1.6 TIMING REQUIREMENTS (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1) tc(SCLK2) twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) tsu(RXD-SCLK1) tsu(SIN2-SCLK2) th(SCLK1-RXD) th(SCLK2-SIN2) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width INT0 to INT4 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input "H" pulse width (Note) Serial I/O2 clock input "H" pulse width Serial I/O1 clock input "L" pulse width (Note) Serial I/O2 clock input "L" pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time Min. 2 125 50 50 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is "1". Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0". Table 3.1.7 TIMING REQUIREMENTS (2) (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1) tc(SCLK2) twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) tsu(RXD-SCLK1) tsu(SIN2-SCLK2) th(SCLK1-RXD) th(SCLK2-SIN2) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width INT0 to INT4 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input "H" pulse width (Note) Serial I/O2 clock input "H" pulse width Serial I/O1 clock input "L" pulse width (Note) Serial I/O2 clock input "L" pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time Parameter Min. 2 500/ (3 VCC-8) 200/ (3 VCC-8) 200/ (3 VCC-8) 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 300 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is "1". Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is "0".
3802 GROUP USER'S MANUAL
3-5
APPENDIX
3.1 Electrical characteristics
Table 3.1.8 SWITCHING CHARACTERISTICS (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) td(SCLK1-TXD) td(SCLK2-SOUT2) tv(SCLK1-TXD) tv(SCLK2-SOUT2) tr(SCLK1) tf(SCLK1) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O2 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O2 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Min. tc(SCLK1)/2-30 tc(SCLK2)/2-160 tc(SCLK1)/2-30 tc(SCLK2)/2-160 140 200 Fig. 3.1.1 -30 0 30 30 30 40 30 30 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10 10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is "0". 3: XOUT pin is excluded. Table 3.1.9 SWITCHING CHARACTERISTICS (2) (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) td(SCLK1-TXD) td(SCLK2-SOUT2) tv(SCLK1-TXD) tv(SCLK2-SOUT2) tr(SCLK1) tf(SCLK1) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O2 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O2 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Min. tc(SCLK1)/2-50 tc(SCLK2)/2-240 tc(SCLK1)/2-50 tc(SCLK2)/2-240 350 400 Fig. 3.1.1 -30 0 50 50 50 50 50 50 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
20 20
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is "0". 3: XOUT pin is excluded.
3-6
3802 GROUP USER'S MANUAL
APPENDIX
3.1 Electrical characteristics
Table 3.1.10 TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tsu(ONW-) th(-ONW) tsu(DB-) th(-DB) tsu(ONW-RD) tsu(ONW-WR) th(RD-ONW) th(WR-ONW) tsu(DB-RD) th(RD-DB) Before  ONW input set up time After  ONW input hold time Before  data bus set up time After  data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time Parameter Limits Min. -20 -20 60 0 -20 -20 65 0 Typ. Max. Unit ns ns ns ns ns ns ns ns
Table 3.1.11 SWITCHING CHARATERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tc() twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) tv(-SYNC) td(-WR) tv(-WR) td(-DB) tv(-DB) Parameter Test conditions Limits Min. tc(XIN)-10 tc(XIN)-10 6 6 20 10 25 10 20 10 10 5 20 40 45 Typ. 2tc(XIN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tc(XIN)-15 tc(XIN)-20 5 5 15 10 0 200 200 65 ns ns ns ns ns ns ns ns
 clock cycle time  clock "H" pulse width  clock "L" pulse width After  AD15-AD8 delay time After  AD15-AD8 valid time After  AD7-AD0 delay time After  AD7-AD0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After  data bus delay time After  data bus valid time RD pulse width, WR pulse width twL(RD) RD pulse width, WR pulse width twL(WR) (When one-wait is valid) td(AH-RD) After AD15-AD8 RD delay time td(AH-WR) After AD15-AD8 WR delay time td(AL-RD) After AD7-AD0 RD delay time td(AL-WR) After AD7-AD0 WR delay time tv(RD-AH) After RD AD15-AD8 valid time tv(WR-AH) After WR AD15-AD8 valid time tv(RD-AL) After RD AD7-AD0 valid time tv(WR-AL) After WR AD7-AD0 valid time td(WR-DB) After WR data bus delay time tv(WR-DB) After WR data bus valid time td(RESET-RESETOUT) RESETOUT output delay time (Note 1) tv(-RESET) RESETOUT output valid time (Note 1)
3 15 tc(XIN)-10 3tc(XIN)-10 tc(XIN)-35 tc(XIN)-40 0 0
20 10 70
Fig. 3.1.1
Note 1: The RESETOUT output goes "H" in sync with the rise of the  clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H".
3802 GROUP USER'S MANUAL
3-7
APPENDIX
3.1 Electrical characteristics
Table 3.1.12 TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (2) (VCC = 3.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tsu(ONW-) th(-ONW) tsu(DB-) th(-DB) tsu(ONW-RD) tsu(ONW-WR) th(RD-ONW) th(WR-ONW) tsu(DB-RD) th(RD-DB) Before  ONW input set up time After  ONW input hold time Before  data bus set up time After  data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time Parameter Min. -20 -20 180 0 -20 -20 185 0 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns
Table 3.1.13 SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (2) (VCC = 3.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tc() twH() twL() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-SYNC) tv(-SYNC) td(-WR) tv(-WR) td(-DB) tv(-DB) Parameter Test conditions Min. Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 195 300 300 ns ns
 clock cycle time 2tc(XIN)  clock "H" pulse width tc(XIN)-20  clock "L" pulse width tc(XIN)-20 After  AD15-AD8 delay time After  AD15-AD8 valid time 15 10 After  AD7-AD0 delay time After  AD7-AD0 valid time 15 10 SYNC delay time 40 SYNC valid time 20 RD and WR delay time 15 RD and WR valid time 7 3 After  data bus delay time After  data bus valid time 15 Fig. 3.1.1 RD pulse width, WR pulse width tc(XIN)-20 twL(RD) RD pulse width, WR pulse width twL(WR) 3tc(XIN)-20 (when one-wait is valid) td(AH-RD) After AD15-AD8 RD delay time tc(XIN)-145 td(AH-WR) After AD15-AD8 WR delay time td(AL-RD) After AD7-AD0 RD delay time tc(XIN)-145 td(AL-WR) After AD7-AD0 WR delay time tv(RD-AH) After RD AD15-AD8 valid time 10 5 tv(WR-AH) After WR AD15-AD8 valid time tv(RD-AL) After RD AD7-AD0 valid time 10 5 tv(WR-AL) After WR AD7-AD0 valid time td(WR-DB) After WR data bus delay time tv(WR-DB) After WR data bus valid time 10 td(RESET-RESETOUT) RESETOUT output delay time (Note 1) tv(-RESET) RESETOUT output valid time (Note 1) 0 Note1: The RESETOUT output goes "H" in sync with the fall of the  clock that is anywhere between about 8 cycle and the RESET input goes "H".
150 150
25 15 200
ns ns 13 cycles after
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3802 GROUP USER'S MANUAL
APPENDIX
3.1 Electrical characteristics
3.1.7 Absolute maximum ratings (Extended operating temperature version)
Table 3.1.14 Absolute maximum ratings (Extended operating temperature version) Symbol Parameter Conditions VCC Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, VI P60-P67, VREF All voltage are based on VSS. VI Input voltage RESET, XIN Output transistors are cut off. VI Input voltage CNVSS Output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, VO P60-P67, XOUT Pd Power dissipation Ta = 25 C Topr Operating temperature Tstg Storage temperature Note: 300mW in case of the flat package Ratings -0.3 to 7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to 13 -0.3 to VCC +0.3 1000 (Note) -40 to 85 -65 to 150 Unit V V V V V mW C C
3.1.8 Recommended operatinmg conditions (Extended operating temperature version)
Table 3.1.15 Recommended operating conditions (Extended operating temperature version) (VCC = 4.0 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. 5.5 VCC 4.0 V 5.0 Power source voltage (f(XIN)  2 MHz) VSS V 0 Power source voltage VCC 2.0 Analog reference voltage (when A-D converter is used) V VREF 4.0 VCC Analog reference voltage (when D-A converter is used) AVSS 0 V Analog power source voltage VIA AVSS VCC V Analog input voltage AN0-AN7 VIH VIH VIL VIL VIL IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) "H" input voltage "H" input voltage "L" input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 RESET, XIN, CNVSS 0.8 VCC 0.8 VCC 0 0 0 VCC VCC 0.2 VCC 0.2 VCC 0.16 VCC -80 -80 80 80 -40 -40 40 40 -10 10 -5 5 8 V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 "L" input voltage RESET, CNVSS "L" input voltage XIN "H" total peak output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) "H" total peak output current P40-P47,P50-P57, P60-P67 (Note 1) "L" total peak output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) "L" total peak output current P40-P47,P50-P57, P60-P67 (Note 1) "H" total average output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) "H" total average output current P40-P47,P50-P57, P60-P67 (Note 1) "L" total average output current P00-P07, P10-P17, P20-P27, P30-P37 (Note 1) "L" total average output current P40-P47,P50-P57, P60-P67 (Note 1) "H" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 (Note 2) "L" peak output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 (Note 2) "H" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 (Note 3) "L" average output current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 (Note 3) Internal clock oscillation frequency (VCC = 4.0 to 5.5 V)
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
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3.1 Electrical characteristics
3.1.9 Electrical characteristics (Extended operating temperature version)
Table 3.1.16 Electrical characteristics (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 (Note 1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,P50-P57, P60-P67 Hysteresis CNTR0, CNTR1, INT0-INT4 Hysteresis RXD, SCLK1, SIN2, SCLK2 Hysteresis RESET "H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, RESET, CNVSS "L" input current XIN RAM hold voltage Test conditions IOH = -10 mA Limits Min. VCC-2.0 Typ. Max. Unit V
VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH IIL IIL VRAM
IOL = 10 mA 0.4 0.5 0.5 VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS When clock stopped f(XIN) = 8 MHz f(XIN) = 5 MHz When WIT instruction is executed with f(XIN) = 8 MHz When WIT instruction is executed with f(XIN) = 5 MHz When STP instruction Ta = 25 C is executed with clock (Note 2) stopped, output Ta = 85 C transistors isolated. (Note 2) -4 2.0 6.4 4 1.5 1 0.1
2.0
V V V V
5.0 5.0 4 -5.0
A A A A A V
5.5 13 8
mA
ICC
Power source current
1 10
A
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is "0". 2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
3.1.10 A-D converter characteristics (Extended operating temperature version)
Table 3.1.17 A-D CONVERTER CHARACTERISTICS (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = -40 to 85 C, unless otherwise noted) Symbol -- -- tCONV RLADDER IVREF II(AD) Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current Test conditions Min. Limits Typ. 1 35 150 0.5 Max. 8 2.5 50 200 5.0 Unit Bits LSB tC() k A A
VREF = 5.0 V
50
Note: When D-A conversion registers (addresses 003616 and 003716) contain "0016".
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3.1 Electrical characteristics
3.1.11 D-A converter characteristics (Extended operating temperature version)
Table 3.1.18 D-A CONVERTER CHARACTERISTICS (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 4.0 V to VCC, Ta = -40 to 85 C, unless otherwise noted) Symbol -- -- tsu RO IVREF Parameter Resolution Absolute accuracy Setting time Output resistor Reference power source input current (Note) Test conditions Min. Limits Typ. Max. 8 1.0 3 4 3.2 Unit Bits % s k mA
1
2.5
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016", and excluding currents flowing through the A-D resistance ladder.
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3.1 Electrical characteristics
3.1.12 Timing requirements and Switching characteristics (Extended operating temperature version)
Table 3.1.19 Timing requirements (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1) tc(SCLK2) twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) tsu(RXD-SCLK1) tsu(SIN2-SCLK2) th(SCLK1-RXD) th(SCLK2-SIN2) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width INT0 to INT4 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input "H" pulse width (Note) Serial I/O2 clock input "H" pulse width Serial I/O1 clock input "L" pulse width (Note) Serial I/O2 clock input "L" pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time Min. 2 125 50 50 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is "1". Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0".
Table 3.1.20 Switching characteristics (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol twH(SCLK1) twH(SCLK2) twL(SCLK1) twL(SCLK2) td(SCLK1-TXD) td(SCLK2-SOUT2) tv(SCLK1-TXD) tv(SCLK2-SOUT2) tr(SCLK1) tf(SCLK1) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O2 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O2 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Min. tc(SCLK1)/2-30 tc(SCLK2)/2-160 tc(SCLK1)/2-30 tc(SCLK2)/2-160 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
140 200 Fig. 3.1.1 -30 0 30 30 30 40 30 30
10 10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is "0". 3: XOUT pin excluded.
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3.1 Electrical characteristics
Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. tsu(ONW-) Before  ONW input set up time -20 ns th(-ONW) After  ONW input hold time -20 ns tsu(DB-) Before  data bus set up time 60 ns th(-DB) After  data bus hold time 0 ns tsu(ONW-RD) Before RD ONW input set up time -20 ns tsu(ONW-WR) Before WR ONW input set up time th(RD-ONW) After RD ONW input hold time -20 ns th(WR-ONW) After WR ONW input hold time tsu(DB-RD) Before RD data bus set up time 65 ns th(RD-DB) After RD data bus hold time 0 ns
Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Typ. Min. Max. tc() ns  clock cycle time 2!tc(XIN) ns twH()  clock "H" pulse width tc(XIN)-10 ns  clock "L" pulse width tc(XIN)-10 twL() 40 ns After  AD15-AD8 delay time td(-AH) 20 ns tv(-AH) After  AD15-AD8 valid time 6 10 ns 45 After  AD7-AD0 delay time 25 td(-AL) ns 10 tv(-AL) After  AD7-AD0 valid time 6 ns 20 td(-SYNC) SYNC delay time ns 10 SYNC valid time tv(-SYNC) ns 20 10 RD and WR delay time td(-WR) ns 10 5 RD and WR valid time tv(-WR) 3 ns 70 20 After  data bus delay time td(-DB) ns After  data bus valid time tv(-DB) 15 Fig. 3.1.1 tc(XIN)-10 ns RD pulse width, WR pulse width twL(RD) RD pulse width, WR pulse width ns 3tc(XIN)-10 twL(WR) (when one wait is valid) td(AH-RD) td(AH-WR) td(AL-RD) td(AL-WR) tv(RD-AH) tv(WR-AH) tv(RD-AL) tv(WR-AL) td(WR-DB) tv(WR-DB) td(RESET-RESETOUT) tv(-RESET) After AD15-AD8 RD delay time After AD15-AD8 WR delay time After AD7-AD0 RD delay time After AD7-AD0 WR delay time After RD AD15-AD8 valid time After WR AD15-AD8 valid time tc(XIN)-35 tc(XIN)-40 0 tc(XIN)-15 tc(XIN)-20 5 ns ns ns
After RD AD7-AD0 valid time ns 5 0 After WR AD7-AD0 valid time ns After WR data bus delay time 65 15 ns After WR data bus valid time 10 ns RESETOUT output delay time 200 ns RESETOUT output valid time (Note 1) 200 0 Note 1: The RESETOUT output goes "H" in sync with the rise of the  clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H".
Measurement output pin 100pF
CMOS output
Fig. 3.1.1 Circuit for measuring output switching characteristics
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APPENDIX
3.1 Electrical characteristics
3.1.13 Timing diagram Timing Diagram
tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2 VCC
CNTR0, CNTR1
0.8 VCC
tWH(INT)
tWL(INT) 0.2 VCC
INT0-INT4
0.8 VCC
tW(RESET)
RESET
0.2 VCC
0.8 VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2 VCC
XIN
0.8 VCC
tf
tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) tr 0.2 VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2) 0.8 VCC
SCLK1 SCLK2
th(SCLK1-RXD), th(SCLK2-SIN2)
RXD SIN2
0.8 VCC 0.2 VCC td(SCLK1-TXD),td(SCLK2-SOUT2) tv(SCLK1-TXD), tv(SCLK2-SOUT2)
TXD SOUT2
Fig. 3.1.2 Timing diagram (in single-chip mode)
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3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode (1)
tC() tWH() tWL()

0.5 VCC
td(-AH)
tv(-AH)
0.5 VCC
AD15-AD8
td(-AL)
tv(-AL)
0.5 VCC
AD7-AD0
td(-SYNC)
tv(-SYNC)
SYNC
0.5 VCC
td(-WR)
tv(-WR)
RD,WR
tSU(ONW-)
0.5 VCC
th(-ONW)
ONW
0.8 VCC 0.2 VCC
tSU(DB-)
th(-DB)
DB0-DB7 (At CPU reading) DB0-DB7 (At CPU writing)
0.8 VCC 0.2 VCC
td(-DB)
0.5 VCC
tv(-DB)
Timing Diagram in Microprocessor Mode
RESET 
0.8 VCC 0.2 VCC
0.5 VCC
td(RESET- RESET OUT)
tv(- RESETOUT)
RESETOUT
0.5 VCC
Fig. 3.1.3 Timing diagram (in memory expansion mode and microprocessor mode) (1)
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3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode (2)
tWL(RD) tWL(WR)
RD,WR
td(AH-RD) td(AH-WR)
0.5 VCC
tv(RD-AH) tv(WR-AH)
AD15-AD8
0.5 VCC
td(AL-RD) td(AL-WR)
tv(RD-AL) tv(WR-AL)
AD7-AD0
0.5 VCC
tsu(ONW-RD) tsu(ONW-WR)
th(RD-ONW) th(WR-ONW)
ONW (At CPU reading) RD
0.8 VCC 0.2 VCC
tWL(RD)
0.5 VCC
tSU(DB-RD)
th(RD-DB)
DB0-DB7
0.8 VCC 0.2 VCC
(At CPU writing) WR
td(WR-DB)
0.5 VCC
tWL(WR)
tv(WR-DB)
0.5 VCC
DB0-DB7
Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (2)
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3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current characteristic examples Figures 3.2.1 and Figure 3.2.2 show power source current characteristic examples.
[Measuring condition : 25 C, A-D conversion stopped]
Rectangular waveform
Power source current 8 (mA) 7 6 5 4 3 2 1 0 Vcc = 4.0V, Ta = 25 c Vcc = 5.5V, Ta = 25 c
0
1
2
3
4
5
6
7
8 Frequency f(XIN) (MHz)
Fig. 3.2.1 Power source current characteristic example
[Measuring condition : 25 C, A-D conversion stopped]
Rectangular waveform
Power source current (mA) 8 7 6 5 4 3 2 1 0 Vcc = 5.5V, Ta = 25 c Vcc = 4.0V, Ta = 25 c 0 1 2 3 4 5 6 7 8 Frequency f(XIN) (MHz)
Fig. 3.2.2 Power source current characteristic example (in wait mode)
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APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristic examples Figures 3.2.3, Figure 3.2.4, Figure 3.2.5 and Figure 3.2.6 show port standard characteristic examples.
[Port 60 IOH-VOH characteristic (P-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6)
IOH (mA)
-50 -45 -40 -35 -30 -25 -20 -15 -10 -5
V cc = 5.5V Ta = 90 c Vcc = 5.0V Ta = 90 c
Vcc = 3.0V Ta = 90 c
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
VOH (V)
Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive (1)
[Port 60 IOH-VOH characteristic (P-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6)
IOH (mA)
-50 -45 -40 -35 -30 -25 -20 -15 -10 -5
Vcc = 5.5V Ta = 25 c Vcc = 5.0V Ta = 25 c
Vcc = 3.0V Ta = 25 c
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VO H (V)
Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive (2)
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3.2 Standard characteristics
[Port 60 IOL-VOL characteristic (N-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6)
IOL (mA)
50 45 40 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V cc = 5.5V Ta = 90 c
V cc = 5.0V Ta = 90 c
V cc = 3.0V Ta = 90 c
VOL (V)
Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive (1)
[Port 60 IOL-VOL characteristic (N-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6)
IOL (mA)
60 55 50 45 40 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V cc = 5.5V Ta = 25c
V cc = 5.0V Ta = 25 c
V cc = 3.0V Ta = 25 c
VOL (V)
Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive (2)
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APPENDIX
3.2 Standard characteristics
3.2.3 A-D conversion standard characteristics Figure 3.2.7 shows the A-D conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error. It represents the deviation from the ideal value. For example, the conversion of output code from 127 to 128 occurs ideally at the point of AN0 = 2550 mV, but the measured value is -5 mV. Accordingly, the measured point of conversion is represented as "2550 - 5 = 2545 mV." The upper-side line on the graph indicates the width of input voltages equivalent to output codes. For example, the measured width of the input voltage for output code 170 is 23 mV, so the differential nonlinear error is represented as "23 - 20 = 3 mV" (0.15 LSB).
M38027E8SS A-D CONVERTER STEP WIDTH MEASUREMENT
Measured when a power source voltage is stable in the single-chip mode Fig. 3.2.7 A-D conversion standard characteristics
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3.2 Standard characteristics
3.2.4 D-A conversion standard characteristics Figure 3.2.8 shows the D-A conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error. In this case, it represents the difference between the ideal analog output value for an input code and the measured value. The upper-side line on the graph indicates the change width of output analog value to a one-bit change of input code.
M38027E8SS D-A CONVERTER STEP WIDTH MEASUREMENT
Measured when a power source voltage is stable in the single-chip mode Fig. 3.2.8 D-A conversion standard characteristics
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APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts (1) Sequence for switching an external interrupt detection edge When the external interrupt detection edge must be switched, make sure the following sequence. Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals. This may cause an unnecessary interrupt. Clear an interrupt enable bit to "0" (interrupt disabled) Switch the detection edge Clear an interrupt request bit to "0" (no interrupt request issued) Set the interrupt enable bit to "1" ( interrupt enabled )
(2) Bit 7 of the interrupt control register 2 Fix the bit 7 of the interrupt control register 2 (Address:003F16) to "0". Figure 3.3.1 shows the structure of the interrupt control register 2.
b7
b0 Interrupt control register 2 Address 003F16
0
Interrupt enable bits Not used Fix this bit to "0"
Fig. 3.3.1 Structure of interrupt control register 2 3.3.2 Notes on the serial I/O1 (1) Stop of data transmission As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the transmit enable bit to "0" (transmit disabled), and clear the serial I/O enable bit to "0" (serial I/O1 disabled)in the following cases : q when stopping data transmission during transmitting data in the clock synchronous serial I/O mode q when stopping data transmission during transmitting data in the UART mode q when stopping only data transmission during transmitting and receiving data in the UART mode Reason Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O1 enable bit is cleared to "0" (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1, ______ and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, the data is transferred to the transmit shift register and start to be shifted. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD pin and ti may cause an operation failure to a microcomputer. (2) Stop of data reception As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the receive enable bit to "0" (receive disabled), or clear the serial I/O enable bit to "0" (serial I/O disabled) in the following case : q when stopping data reception during receiving data in the clock synchronous serial I/O mode Clear the receive enable bit to "0" (receive disabled) in the following cases : q when stopping data reception during receiving data in the UART mode q when stopping only data reception during transmitting and receiving data in the UART mode
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3.3 Notes on use
(3) Stop of data transmission and reception in a clock synchronous serial I/O mode As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled) at the same time in the following case: q when stopping data transmission and reception during transmitting and receiving data in the clock synchronous mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to "0" (serial I/O1 disabled) (refer to (1)).
_____
(4) The SRDY pin on a receiving side _____ When signals are output from the SRDY pin on the reception_____by using an external clock in the clock side synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and the transmit enable bit to "1" (transmit enabled). (5) Stop of data reception in a clock synchronous serial I/O mode Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE) to "1"
Can be set with the LDM instruction at the same time
(6) Control of data transmission using the transmit shift completion flag The transmit shift completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When checking the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data transmission, note this delay. (7) Control of data transmission using an external clock When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" level of the SCLK input signal. Also, write data to the transmit buffer register at "H" level of the SCLK input signal.
3.3.3 Notes on the A-D converter (1) Input of signals from signal source with high impedance to an analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 F to 1 F. Further, maek sure to check the operation of application products on the user side. Reason The A-D converter builds in the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, a charge and discharge noise generates. This may cause the A-D conversion precision to be worse.
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APPENDIX
3.3 Notes on use
(2) AVSS pin Connect a power source for the A-D converter, AVSS pin to the VSS line of the analog circuit. (3) A clock frequency during an A-D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A-D conversion. q f(XIN) is 500 kHz or more . (When the ONW pin is "L", f(XIN) is 1 MHz or more.) q Do not execute the STP instruction and WIT instruction.
3.3.4 Notes on the RESET pin When a rising time of the reset signal is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, make sure the following : qMake the length of the wiring which is connected to a capacitor the shortest possible. qMake sure to check the operation of application products on the user side. Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, a microcomputer may malfunction.
3.3.5 Notes on input and output pins (1) Fix of a port input level in stand-by state Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state, especially for the I/O ports of the N-channel open-drain. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, make sure the following: qExternal circuit qVariation of output levels during the ordinary operation * stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
Reason Even when setting as an output port with its direction register, in the following state : qN-channel.when the content of the port latch is "1" the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the level becomes "undefined" depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an I/O port are "undefined." This may cause power source current. (2) Modify of the content of I/O port latch When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the unspecified bit may be changed. Reason The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit. Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed to all bits of the port latch. qAs for a bit which is set as an input port : The pin state is read in the CPU, and is written to this bit after bit managing. qAs for a bit which is set as an output port : The bit value is read in the CPU, and is written to this bit after bit managing.
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3.3 Notes on use
Make sure the following : qEven when a port which is set as an output port is changed for an input port, its port latch holds the output data. qEven when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction, its value may be changed in case where content of the pin differs from a content of the port latch. * bit managing instructions : SEB and CLB instruction (3) The AVSS pin when not using the A-D converter When not using the A-D converter, handle a power source pin for the A-D converter, AVSS pin as follows : q AVSS : Connect to the VSS pin Reason If the AVSS pin is opened, the microcomputer may malfunction by effect of noise or others.
3.3.6 Notes on memory expansion mode and microprocessor mode (1) Writing data to the port latch of port P3 In the memory expansion or the microprocessor mode, ports P30 and P31 can be used as the output port. Use the LDM or STA instruction for writing data to the port latch (address 000616) of port P3. When using a read-modify-write instruction (the SEB or the CLB instruction), allocate the read and the write enabled memory at address 000616. Reason In the memory expansion or microprocessor mode, address 000616 is allocated in the external area. Accordingly, q Data is read from the external memory. q Data is written to both the port latch of the port P3 and the external memory. Accordingly, when executing a read-modify-write instruction for address 000616, external memory data is read and modified, and the result is written in both the port latch of the port P3 and the external memory. If the read enabled memory is not allocated at address 000616, the read data is undefined. The undefined data is modified and written to the port latch of the port P3. The port latch data of port P3 becomes "undefined." (2) Overlap of an internal memory and an external memory When the internal and the external memory are overlapped in the memory expansion mode, the internal memory is valid in this overlapped area. When the CPU writes or reads to this area, the following is performed : q When reading data Only the data in the internal memory is read into the CPU and the data in the external memory is not read into the CPU. However, as the read signal and address are still valid, the external memory data of the corresponding address is output to the external data bus. q When writing data Data is written in both the internal and the external memory.
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APPENDIX
3.3 Notes on use
3.3.7 Notes on built-in PROM (1) Programming adapter To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose PROM programmer as shown in Table 3.3.1. Table 3.3.1 Programming adapter Microcomputer M38027E8SS M38027E8SP (one-time blank) M38027E8DSP (one-time blank) M38027E8FS M38027E8FP (one-time blank) M38027E8DFP (one-time blank) (2) Write and read In PROM mode, operation is the same as that of the M5M27C256AK and the M5M27C101, but programming conditions of PROM programmer are not set automatically because there are no internal device ID codes. Accurately set the following conditions for data write/read. Take care not to apply 21 V to Vpp pin (is also used as the CNVSS pin), or the product may be permanently damaged. q Programming voltage : 12.5 V q Setting of programming adapter switch : refer to table 3.3.2 q Setting of PROM programmer address : refer to table 3.3.3 Table 3.3.2 Setting of programming adapter switch Programming adapter PCA4738S-64A PCA4738L-64A PCA4738F-64A CMOS CMOS OFF SW 1 SW 2 SW 3 PCA4738F-64A PCA4738L-64A PCA4738S-64A Programming adapter
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3.3 Notes on use
Table 3.3.3 Setting of PROM programmer address Microcomputer M38022E4SS M38022E4SP M38022E4FS Address : 408016 (Note 1) M38022E4FP M38022E4DSP M38022E4DFP M38027E8SS M38027E8SP M38027E8FS M38027E8FP M38027E8DSP M38027E8DFP Note1 : Addresses C08016 to FFFD16 in the internal PROM correspond to addresses 408016 to 7FFD16 in the ROM programmer. 2 : Addresses 808016 to FFFD16 in the internal PROM correspond to addresses 008016 to 7FFD16 in the ROM programmer. (3) Erasing Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537Angstrom . At least 15 W-sec/cm 2 are required to erase EPROM contents. Address : 008016 (Note 2) Address : 7FFD16 (Note 2) Address : 7FFD16 (Note 1) PROM programmer start address PROM programmer completion address
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APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for the RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). Reason The reset works to initialize a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset circuit VSS
RESET VSS
Reset circuit VSS
RESET VSS
N.G.
3802 group
O.K.
3802 group
Fig. 3.4.1 Wiring for the RESET pin (2) Wiring for clock input/output pins qMake the length of wiring which is connected to clock I/O pins as short as possible. qMake the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillatorand the VSS pin of a microcomputer as short as possible. qSeparate the VSS pattern only for oscillation from other VSS patterns. Reason A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
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3.4 Countermeasures against noise
Noise
An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example
XIN XOUT VSS
XIN XOUT VSS
XIN XOUT VSS
N.G.
Fig. 3.4.2 Wiring for clock I/O pins
O.K.
Separate the VSS line for oscillation from other VSS lines
(3) Wiring for the VPP pin of the One Time PROM version and the EPROM version (In this microcomputer the VPP pin is also used as the CNVSS pin) Connect an approximately 5 k resistor to the V P P pin the shortest possible in series and also to the VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest possible. Note:Even when a circuit which inclued an approximately 5 k resistor is used in the Mask ROM version, the maicrocomputer operates correctly. Reason The VPP pin of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal in struction codes or data are read from the built-in PROM, which may cause a program runaway.
Approximately 5k CNVSS/VPP VSS
3802 group
Make it the shortest possible
Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version
3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: qConnect a bypass capacitor across the VSS pin and the VCC pin at equal length . qConnect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. qUse lines with a larger diameter than other signal lines for VSS line and VCC line.
VCC Chip VCC VSS
VSS
Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line
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3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins qConnect an approximately 100  to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. qConnect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. Reason Signals which is input in an analog input pin (such as an A-D converter input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Noise
(Note)
Microcomputer Analog input pin
Thermistor
N.G.
O.K.
VSS
Note:The resistor is for dividing resistance with a thermister. Fig.3.4.5 Analog signal line and a resistor and a capacitor
3.4.4. Consideration for oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Keeping an oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an osillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin line) may affect other lines at signal rising or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway.
Microcomputer Mutual inductance M Large current GND Fig.3.4.6 Wiring for a large current signal line XIN XOUT VSS
Do not cross
CNTR XIN XOUT VSS
Fig.3.4.7 Wiring to a signal line where potential levels change frequently
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3.4 Countermeasures against noise
3.4.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware> qConnect a resistor of 100  or more to an I/O port inseries.
O.K.
Data bus
Direction register
Noise
Noise
<Software> qAs for an input port, read data several times by a Port latch program for checking whether input levels are I/O port pins equal or not. qAs for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. Fig. 3.4.8 Setup for I/O ports qRewirte data to direction registers and pull-up control registers (only the product having it) at fixed periods. When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. 3.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
N.G.
Main routine (SWDT) N CLI Main processing N (SWDT) =N? =N Interrupt processing
Interrupt processing routine (SWDT)  (SWDT)--1 Interrupt processing >0 RTI Return Main routine
(SWDT) 0? 0
<The main routine> routine errors errors qAssigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. Fig. 3.4.9 Watchdog timer by software The initial value N should satisfy the following condition: N+1  (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. qWatches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing count after the initial value N has been set. qDetects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: If the SWDT contents do not change after interrupt processing
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APPENDIX
3.4 Countermeasures against noise
<The interrupt processing routine> qDecrements the SWDT contents by 1 at each interrupt processing. qDetermins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). qDetects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value N.
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3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6) [Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16]
B 0 Port Pi0 1 Port Pi1
Name
q
Function
In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins
At reset
RW
? ? ? ? ? ? ? ?
q
2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7
Fig. 3.5.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6) [Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16]
B
Name
Function
0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
At reset
RW
! ! ! ! ! ! ! !
0 Port Pi direction register 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Fig. 3.5.2 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6)
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APPENDIX
3.5 List of registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816] Function B 0 A transmission data is written to or a receive data is read out 1 2 3 4 5 6 7
At reset
RW
from this buffer register. * At writing : a data is written to the Transmit buffer register. * At reading : a content of the Receive buffer register is read out.
? ? ? ? ? ? ? ?
Fig. 3.5.3 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 status register (SIO1STS) [Address : 1916]
Name B Transmit buffer empty flag 0
(TBE)
Function
0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : (OE) (PE) (FE) = 0 1 : (OE) (PE) (FE) = 1
At reset
0 0 0 0 0 0 0 1
RW ! ! ! ! ! ! ! !
1 Receive buffer full flag (RBF) 2 Transmit shift register shift
completion flag (TSC)
3 Overrun error flag (OE) 4 Parity error flag (PE) 5 Framing error flag (FE) 6 Summing error flag (SE)
7 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is "0."
Fig. 3.5.4 Structure of Serial I/O1 status register
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3.5 List of registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON) [Address : 1A16]
B
Name
Function
At reset
RW
0 BRG count source selection bit (CSS) 1
2 3 4 5 6 7
0 : f(XIN) 1 : f(XIN)/4 Serial I/O1 synchronous clock At selecting clock synchronous serial I/O selection bit (SCS) 0 : BRG output divided by 4 1 : External clock input At selecting UART 0 : BRG output divided by 16 1 : External clock input divided by 16 SRDY1 output enable bit 0 : I/O port (P47) (SRDY) 1 : SRDY1 output pin 0 : Transmit buffer empty Transmit interrupt 1 : Transmit shift operating completion source selection bit (TIC) 0 : Transmit disabled Transmit enable bit (TE) 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled 0 : UART Serial I/O1 mode 1 : Clock synchronous serial I/O selection bit (SIOM) Serial I/O1 enable bit (SIOE) 0 : Serial I/O1 disabled (P44-P47 : I/O port) 1 : Serial I/O1 enabled (P44-P47 : Serial I/O function pin)
0 0
0 0 0 0 0 0
Fig. 3.5.5 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address : 1B16]
B 0 1 2 3 4 5 6 7
Name
Character length selection bit (CHAS) Parity enable bit (PARE) Parity selection bit (PARS) Stop bit length selection bit (STPS) P45/TxD P-channel output disable bit (POFF)
Function
At reset
RW
0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : Even parity 1 : Odd parity 0 : 1 stop bit 1 : 2 stop bits In output mode 0 : CMOS output 1 : N-channel open-drain output Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "1."
0 0 0 0 0 1 1 1
Fig. 3.5.6 Structure of UART control register
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APPENDIX
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C16]
B
Function
At reset
RW
0 A count value of Baud rate generator is set. 1 2 3 4 5 6 7
? ? ? ? ? ? ? ?
Fig. 3.5.7 Structure of Baud rate generator
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 control register (SIO2CON) [Address : 1D16]
Name B 0 Internal synchronous clock
selection bits
Function
b2 b1 b0
At reset
RW
0 0 0 0 0 0 0 0
1 2 3 Serial I/O2 port selection bit 4 5 6 7
0 0 0 0 1 1
0 0 1 1 1 1
0 : f(XIN)/8 1 : f(XIN)/16 0 : f(XIN)/32 1 : f(XIN)/64 0 : f(XIN)/128 1 : f(XIN)/256
0 : I/O port (P51, P52) 1 : SOUT2, SCLK2 output pin 0 : I/O port (P53) SRDY2 output enable bit 1 : SRDY2 output pin Transfer direction selection bit 0 : LSB first 1 : MSB first Serial I/O2 synchronous clock 0 : External clock 1 : Internal clock selection bit In output mode P51/SOUT2 P-channel 0 : CMOS output output disable bit
1 : N-channel open-drain output
Fig. 3.5.8 Structure of Serial I/O2 control register
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3.5 List of registers
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 register (SIO2) [Address : 1F16]
B
q
Function
At reset
RW
0 A shift register for serial transmission and reception.
At transmitting : Set a transmission data. q At receiving : Store a reception data. 1
? ? ? ? ? ? ? ?
2 3 4 5 6 7
Fig. 3.5.9 Structure of Serial I/O2 register
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY) [Address : 2016, 2416, 2616]
B 0 1 2 3 4 5 6 7
Function
q q q
At reset
RW
The count value of each prescaler is set. The value set in this register is written to both the prescaler and the prescaler latch at the same time. When the prescaler is read out, the value (count value) of the prescaler is read out.
1 1 1 1 1 1 1 1
Fig. 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y
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APPENDIX
3.5 List of registers
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 2116]
B 0 1 2 3 4 5 6 7
Function
q q q
At reset
RW
The count value of the Timer 1 is set. The value set in this register is written to both the Timer 1 and the Timer 1 latch at the same time. When the Timer 1 is read out, the value (count value) of the Timer 1 is read out.
1 0 0 0 0 0 0 0
Fig. 3.5.11 Structure of Timer 1
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2), Timer X (TX), Timer Y (TY) [Address : 2216, 2516, 2716]
B 0 1 2 3 4 5 6 7
q q q
Function
The count value of each timer is set. The value set in this register is written to both the Timer and the Timer latch at the same time. When the Timer is read out, the value (count value) of the Timer is read out.
At reset
RW
1 1 1 1 1 1 1 1
Fig. 3.5.12 Structure of Timer 2, Timer X, Timer Y
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3.5 List of registers
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer XY mode register (TM) [Address : 2316]
Name B 0 Timer X operating mode 1 2 CNTR0 active edge switch
bit 3 Timer X count stop bit
Function
b1 b0
At reset
RW
0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode It depends on the operating mode of the Timer X (refer to Table 3.5.1). 0 : Count start 1 : Count stop
b5 b4
0 0 0 0 0 0 0 0
4 Timer Y operating mode 5 6 CNTR1 active edge switch
bit 7 Timer Y count stop bit
0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode It depends on the operating mode of the Timer Y (refer to Table 3.5.1 ). 0 : Count start 1 : Count stop
Fig. 3.5.13 Structure of Timer XY mode register
Table. 3.5.1 Function of CNTR0/CNTR1 edge switch bit Operating mode of Timer X/Timer Y Timer mode Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6) "0" "1" Pulse output mode "0" "1" Event counter mode "0" "1" Pulse width measurement mode "0" "1" * Generation of CNTR0/CNTR1 interrupt request : Falling (No effect on timer count) * Generation of CNTR0/CNTR1 interrupt request : Rising (No effect on timer count) * Start of pulse output : From "H" level * Generation of CNTR0/CNTR1 interrupt request : Falling * Start of pulse output : From "L" level * Generation of CNTR0/CNTR1 interrupt request : Rising * Timer X/Timer Y : Count of rising edge * Generation of CNTR0/CNTR1 interrupt request : Falling * Timer X/Timer Y : Count of falling edge * Generation of CNTR0/CNTR1 interrupt request : Rising * Timer X/Timer Y : Measurement of "H" level width * Generation of CNTR0/CNTR1 interrupt request : Falling * Timer X/Timer Y : Measurement of "L" level width * Generation of CNTR0/CNTR1 interrupt request : Rising edge edge
edge edge edge edge edge edge
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APPENDIX
3.5 List of registers
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0 PWM control register (PWMCON) [Address:2B16]
B
Name
Function
0 : PWM disabled 1 : PWM enabled 0 : f(XIN) 1 : f(XIN)/2
At reset
RW
0 PWM function enable bit 1 Count source selection bit
0 0 0 0 0 0 0 0
! ! ! ! ! !
2 Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are "0".
3 4 5 6 7
Fig. 3.5.14 Structure of PWM control register
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0 PWM prescaler (PREPWM) [Address : 2C16]
B 0 1 2 3 4 5 6 7
q PWM
Function
cycle is set. q The values set in this register is written to both the PWM prescaler pre-latch and the PWM prescaler latch at the same time. q When data is written during outputting PWM, the pulses corresponding to the changed contents are output starting with the next cycle. q When this register is read out, the content of the PWM prescaler latch is read out.
At reset
RW
? ? ? ? ? ? ? ?
Fig. 3.5.15 Structure of PWM prescaler
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3.5 List of registers
PWM register
b7 b6 b5 b4 b3 b2 b1 b0 PWM register (PWM) [Address : 2D16]
b 0 1 2
Function
q q q
At reset
RW
q
3 4 5 6 7
"H" level output period of PWM is set. The values set in this register is written both the PWM register pre-latch and the PWM register latch at the same time. When data is written during outputting PWM, the pulses corresponding to the changed contents are output starting with the next cycle. When this register is read out, the content of the PWM register latch is read out.
? ? ? ? ? ? ? ?
Fig. 3.5.16 Structure of PWM register
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APPENDIX
3.5 List of registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0 AD/DA control register (ADCON) [Address : 3416]
B
Name
b2 b1 b0
Function
At reset
RW
0 Analog input pin selection bits 0 0 0 : P60/AN0 1 2 3 4 5 6
0 0 1 : P61/AN1 0 1 0 : P62/AN2 0 1 1 : P63/AN3 1 0 0 : P64/AN4 1 0 1 : P65/AN5 1 1 0 : P66/AN6 1 1 1 : P67/AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0." 0 : DA1 output disable DA1 output enable bit 1 : DA1 output enable 0 : DA2 output disabled 1 : DA2 output enabled
0 0 0 1 0 0 0 0
! !
7 DA2 output enable bit
Fig. 3.5.17 Structure of AD/DA control register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address : 3516]
B Function 0 The read-only register which A-D conversion results are stored. 1 2 3 4 5 6 7
At reset
RW
! ! ! ! ! ! ! !
? ? ? ? ? ? ? ?
Fig. 3.5.18 Structure of A-D conversion register
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APPENDIX
3.5 List of registers
D-A1 conversion register, D-A2 conversion register
b7 b6 b5 b4 b3 b2 b1 b0 D-A1 conversion register (DA1), D-A2 conversion register (DA2) [Address : 3616, 3716]
B 0 1 2 3 4 5 6 7
Function
An output value of each D-A converter is set.
At reset
RW
0 0 0 0 0 0 0 0
Fig. 3.5.19 Structure of D-A 1 conversion, D-A 2 conversion register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A16]
Name B INT0 interrupt edge 0
selection bit
Function
0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active
At reset
RW
0 0 0 0 0 0 0 0
1 INT1 interrupt edge 2 3 4 5 6 7
selection bit Nothing is allocated for this bit. This is a write disabled bit.When this bit is read out, the value is "0." INT2 interrupt edge 0 : Falling edge active selection bit 1 : Rising edge active 0 : Falling edge active INT3 interrupt edge 1 : Rising edge active selection bit INT4 interrupt edge 0 : Falling edge active selection bit 1 : Rising edge active Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0."
Fig. 3.5.20 Structure of Interrupt edge selection register
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APPENDIX
3.5 List of registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Adress : 3B16]
B Name 0 Processor mode bits 1 2 Stack page selection bit
Function
00 : Single-chip mode 01 : Memory expansion mode 10 : Microprocessor mode 11 : Not available 0 : 0 page 1 : 1 page
At reset
RW
0
T
0 0 0 0 0 0
! ! ! ! !
3 Nothing is allocated for these bits. These are write disabled bits. 4 When these bits are read out, the values are "0." 5 6 7
T An initial value of bit 1 is determined by a level of the CNVSS pin.
Fig. 3.5.21 Structure of CPU mode register
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APPENDIX
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address : 3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T T
0 INT0 interrupt request bit 1 INT1 interrupt request bit 2 Serial I/O1 receive interrupt
request bit 3 Serial I/O1 transmit interrupt request bit
0 0 0 0 0 0 0 0
4 Timer X interrupt request bit 5 Timer Y interrupt request bit 6 Timer 1 interrupt request bit 7 Timer 2 interrupt request bit
T "0" is set by software, but not "1."
Fig. 3.5.22 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name B 0 CNTR0 interrupt request bit 1 CNTR1 interrupt request bit 2 Serial I/O2 interrupt request
bit
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T T !
0 0 0 0 0 0 0 0
3 INT2 interrupt request bit 4 INT3 interrupt request bit 5 INT4 interrupt request bit 6 AD conversion interrupt
request bit
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0." T "0" is set by software, but not "1."
Fig. 3.5.23 Structure of Interrupt request register 2
3802 GROUP USER'S MANUAL
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APPENDIX
3.5 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1 interrupt enable bit 2 Serial I/O1 receive interrupt
enable bit Serial I/O1 transmit interrupt 3 enable bit
0 0 0 0 0 0 0 0
4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit 7 Timer 2 interrupt enable bit
Fig. 3.5.24 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
Name B 0 CNTR0 interrupt enable bit
Function
At reset
RW
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled CNTR1 interrupt enable bit 1 1 : Interrupt enabled 0 : Interrupt disabled 2 Serial I/O2 interrupt enable bit 1 : Interrupt enabled 0 : Interrupt disabled 3 INT2 interrupt enable bit 1 : Interrupt enabled
0 0 0 0 0 0 0 0
4 INT3 interrupt enable bit 5 INT4 interrupt enable bit 6 AD conversion interrupt
enable bit
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
7 Fix this bit to "0."
Fig. 3.5.25 Structure of Interrupt control register 2
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3802 GROUP USER'S MANUAL
APPENDIX
3.6 Mask ROM ordering method
3.6 Mask ROM ordering method
3802 GROUP USER'S MANUAL
3-47
APPENDIX
3.6 Mask ROM ordering method
3-48
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APPENDIX
3.6 Mask ROM ordering method
3802 GROUP USER'S MANUAL
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APPENDIX
3.6 Mask ROM ordering method
3-50
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APPENDIX
3.6 Mask ROM ordering method
3802 GROUP USER'S MANUAL
3-51
APPENDIX
3.6 Mask ROM ordering method
3-52
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APPENDIX
3.6 Mask ROM ordering method
3802 GROUP USER'S MANUAL
3-53
APPENDIX
3.6 Mask ROM ordering method
3-54
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APPENDIX
3.6 Mask ROM ordering method
3802 GROUP USER'S MANUAL
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APPENDIX
3.6 Mask ROM ordering method
3-56
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APPENDIX
3.6 Mask ROM ordering method
3802 GROUP USER'S MANUAL
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APPENDIX
3.6 Mask ROM ordering method
3-58
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APPENDIX
3.6 Mask ROM ordering method
3802 GROUP USER'S MANUAL
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APPENDIX
3.6 Mask ROM ordering method
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APPENDIX
3.7 Mark specification form
3.7 Mark specification form
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3-61
APPENDIX
3.7 Mark specification form
3-62
3802 GROUP USER'S MANUAL
APPENDIX
3.8 Package outline
3.8 Package outline
3802 GROUP USER'S MANUAL
3-63
APPENDIX
3.8 Package outline
3-64
3802 GROUP USER'S MANUAL
APPENDIX
3.4 List of instruction codes
3.9 List of instruction codes
D3 - D0 Hexadecimal notation 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
D7 - D4
0
1
2
3 BBS 0, A BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A BBC 5, A BBS 6, A BBC 6, A BBS 7, A BBC 7, A
4
5 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X
6 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X
7 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP
8
9 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y -- STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y
A ASL A DEC A ROL A INC A LSR A -- ROR A --
B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A
C
D ORA ABS
E ASL ABS
F SEB 0, ZP
0000
BRK
JSR ORA IND, X ZP, IND ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y CLT JSR SP SET
--
PHP
--
0001
1
BPL JSR ABS BMI
-- BIT ZP -- COM ZP -- TST ZP -- STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP -- CPX ZP --
CLC
-- BIT ABS LDM ZP JMP ABS -- JMP IND -- STY ABS -- LDY ABS
CLB ASL ORA ABS, X ABS, X 0, ZP AND ABS ROL ABS SEB 1, ZP
0010
2
PLP
0011
3
SEC
CLB ROL AND ABS, X ABS, X 1, ZP EOR ABS LSR ABS SEB 2, ZP
0100
4
RTI
STP
PHA
0101
5
BVC
--
CLI
CLB LSR EOR ABS, X ABS, X 2, ZP ADC ABS ROR ABS SEB 3, ZP
0110
6
RTS
ADC MUL IND, X ZP, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X -- RRF ZP -- LDX IMM
PLA
0111
7
BVS
SEI
CLB ROR ADC ABS, X ABS, X 3, ZP STA ABS STA ABS, X LDA ABS STX ABS -- LDX ABS SEB 4, ZP CLB 4, ZP SEB 5, ZP
1000
8
BRA
DEY
TXA
1001
9
BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ
TYA
TXS
1010
A
TAY
TAX
1011
B
LDA JMP IND, Y ZP, IND CMP IND, X CMP IND, Y
WIT
CLV
TSX
CLB LDX LDA LDY ABS, X ABS, X ABS, Y 5, ZP CPY ABS -- CPX ABS -- CMP ABS DEC ABS SEB 6, ZP
1100
C
INY
DEX
1101
D
--
CLD
--
CLB DEC CMP ABS, X ABS, X 6, ZP SBC ABS INC ABS SEB 7, ZP
1110
E
DIV SBC IND, X ZP, X
INX
NOP
1111
F
SBC IND, Y
--
SED
--
CLB INC SBC ABS, X ABS, X 7, ZP
3-byte instruction 2-byte instruction 1-byte instruction
3802 GROUP USER'S MANUAL
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APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 5) When T = 0 AA+M+C When T = 1 M(X)  M(X) + M + C Adds the carry, accumulator and memory contents. The results are entered into the accumulator. Adds the contents of the memory in the address indicated by index register X, the contents of the memory specified by the addressing mode and the carry. The results are entered into the memory at the address indicated by index register X. "AND's" the accumulator and memory contents. The results are entered into the accumulator. "AND's" the contents of the memory of the address indicated by index register X and the contents of the memory specified by the addressing mode. The results are entered into the memory at the address indicated by index register X. Shifts the contents of accumulator or contents of memory one bit to the left. The low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag. Branches when the contents of the bit specified in the accumulator or memory is "0". Branches when the contents of the bit specified in the accumulator or memory is "1". Branches when the contents of carry flag is "0". Branches when the contents of carry flag is "1". Branches when the contents of zero flag is "1". 24 3 2 IMM # OP n 69 2 A # OP n 2 BIT, A # OP n ZP # OP n 65 3 BIT, ZP # OP n 2 #
ASL
C
7
0
0
BBC (Note 4) BBS (Note 4) BCC (Note 4) BCS (Note 4) BEQ (Note 4) BIT
Ab or Mb = 0?
Ab or Mb = 1?
C = 0?
C = 1?
Z = 1? V
A
M
BMI (Note 4) BNE (Note 4) BPL (Note 4) BRA
N = 1?
Z = 0?
N = 0? PC  PC  offset B1 M(S)  PCH SS-1 M(S)  PCL SS-1 M(S)  PS SS-1 PCL  ADL PCH  ADH
BRK
3-66
V
When T = 1 M(X)  M(X)
V
AND (Note 1)
When T = 0 AA M M
29 2
2
25 3
2
0A 2
1
06 5
2
13 4 + 2i 03 4 + 2i
2
17 5 + 2i 07 5 + 2i
3
2
3
"AND's" the contents of accumulator and memory. The results are not entered anywhere. Branches when the contents of negative flag is "1". Branches when the contents of zero flag is "0".
Branches when the contents of negative flag is "0". Jumps to address specified by adding offset to the program counter. Executes a software interrupt. 00 7 1
3802 GROUP USER'S MANUAL
APPENDIX
3.10 Machine instructions
Addressing mode ZP, X OP n 75 4 ZP, Y # OP n 2 ABS # OP n 6D 4 ABS, X # OP n 3 7D 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z Z 0 C C
# OP n 3 79 5
# OP n 3
# OP n 61 6
# OP n 2 71 6
# OP n 2
NV NV
35 4
2
2D 4
3 3D 5
3 39 5
3
21 6
2 31 6
2
N
*
*
*
*
*
Z
*
16 6
2
0E 6
3 1E 7
3
N
*
*
*
*
*
Z
C
*
*
*
*
*
*
*
*
* 90 2 2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
B0 2
2
*
*
*
*
*
*
*
*
F0 2 2C 4 3
2
*
*
*
*
*
*
*
*
M7 M6 *
*
*
*
Z
*
30 2
2
*
*
*
*
*
*
*
*
D0 2
2
*
*
*
*
*
*
*
*
10 2
2
*
*
*
*
*
*
*
*
80 4
2
*
*
*
*
*
*
*
*
*
*
*
1
*
1
*
*
3802 GROUP USER'S MANUAL
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APPENDIX
3.10 Machine instructions
Addressing mode Symbol Function Details IMP OP n BVC (Note 4) BVS (Note 4) CLB V = 0? Branches when the contents of overflow flag is "0". Branches when the contents of overflow flag is "1". Clears the contents of the bit specified in the accumulator or memory to "0". Clears the contents of the carry flag to "0". 18 2 1 1B 2 + 2i 1 1F 5 + 2i 2 IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n #
V = 1? Ab or Mb  0 C0 D0 I0 T0 V0 When T = 0 A-M When T = 1 M(X) - M MM X-M
CLC
CLD
Clears the contents of decimal mode flag to "0". Clears the contents of interrupt disable flag to "0". Clears the contents of index X mode flag to "0". Clears the contents of overflow flag to "0".
D8 2
1
CLI
58 2
1
CLT
12 2
1
CLV
B8 2
1
CMP (Note 3)
Compares the contents of accumulator and memory. Compares the contents of the memory specified by the addressing mode with the contents of the address indicated by index register X. Forms a one's complement of the contents of memory, and stores it into memory. Compares the contents of index register X and memory. Compares the contents of index register Y and memory. Decrements the contents of the accumulator or memory by 1. Decrements the contents of index register X CA 2 by 1. Decrements the contents of index register Y by 1. Divides the 16-bit data that is the contents of M (zz + x + 1) for high byte and the contents of M (zz + x) for low byte by the accumulator. Stores the quotient in the accumulator and the 1's complement of the remainder on the stack. "Exclusive-ORs" the contents of accumulator and memory. The results are stored in the accumulator. "Exclusive-ORs" the contents of the memory specified by the addressing mode and the contents of the memory at the address indicated by index register X. The results are stored into the memory at the address indicated by index register X. Connects oscillator output to the XOUT pin. E2 2 1 88 2 1
C9 2
2
C5 3
2
COM
44 5
2
CPX
E0 2
2
E4 3
2
CPY
Y-M A  A - 1 or MM-1 XX-1 YY-1 A  (M(zz + X + 1), M(zz + X)) / A M(S)  1's complememt of Remainder SS-1 When T = 0 - AAVM When T = 1 - M(X)  M(X) V M
C0 2
2
C4 3
2
DEC
1A 2
1
C6 5
2
DEX
DEY
1
DIV
EOR (Note 1)
49 2
2
45 3
2
FST A  A + 1 or MM+1 XX+1 YY+1
INC
Increments the contents of accumulator or memory by 1. Increments the contents of index register X by 1. Increments the contents of index register Y by 1. E8 2 1
3A 2
1
E6 5
2
INX
INY
C8 2
1
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3802 GROUP USER'S MANUAL
APPENDIX
3.10 Machine instructions
Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n 2 # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n
# OP n
# OP n
# OP n
# OP n 50 2
NV * *
70 2
2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
*
*
*
*
0
*
*
*
*
*
*
*
*
0
*
*
*
*
0
*
*
*
*
*
* D5 4 CD 4 3 DD 5
0
*
*
*
*
*
*
2
3 D9 5
3
C1 6
2 D1 6
2
N
*
*
*
*
*
Z
C
N EC 4 3
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
C
CC 4
3
N 3
*
*
*
*
*
Z
C
D6 6
2
CE 6
3 DE 7
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N E2 16 2
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
55 4
2
4D 4
3 5D 5
3 59 5
3
41 6
2 51 6
2
N
*
*
*
*
*
Z
*
* F6 6 EE 6 3 FE 7 3
*
*
*
*
*
*
*
2
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
3802 GROUP USER'S MANUAL
3-69
APPENDIX
3.10 Machine instructions
Addressing mode Symbol Function Details IMP OP n JMP If addressing mode is ABS PCL  ADL PCH  ADH If addressing mode is IND PCL  M (ADH, ADL) PCH  M (ADH, ADL + 1) If addressing mode is ZP, IND PCL  M(00, ADL) PCH  M(00, ADL + 1) M(S)  PCH SS-1 M(S)  PCL SS-1 After executing the above, if addressing mode is ABS, PCL  ADL PCH  ADH if addressing mode is SP, PCL  ADL PCH  FF If addressing mode is ZP, IND, PCL  M(00, ADL) PCH  M(00, ADL + 1) When T = 0 AM When T = 1 M(X)  M M  nn XM YM Jumps to the specified address. IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n #
JSR
After storing contents of program counter in stack, and jumps to the specified address.
LDA (Note 2)
Load accumulator with contents of memory. Load memory indicated by index register X with contents of memory specified by the addressing mode. Load memory with immediate value.
A9 2
2
A5 3
2
LDM
3C 4 A2 2 A0 2
3
LDX
Load index register X with contents of memory. Load index register Y with contents of memory. 0 C Shift the contents of accumulator or memory to the right by one bit. The low order bit of accumulator or memory is stored in carry, 7th bit is cleared. Multiplies the accumulator with the contents of memory specified by the zero page X addressing mode and stores the high byte of the result on the stack and the low byte in the accumulator. No operation. EA 2 1
2
A6 3
2
LDY
2 4A 2 1
A4 3
2
LSR
7 0
46 5
2
MUL (Note 5)
M(S) * A  A ! M(zz + X) SS-1
NOP
PC  PC + 1 When T = 0 AAVM When T = 1 M(X)  M(X) V M
ORA (Note 1)
"Logical OR's" the contents of memory and accumulator. The result is stored in the accumulator. "Logical OR's" the contents of memory indicated by index register X and contents of memory specified by the addressing mode. The result is stored in the memory specified by index register X.
09 2
2
05 3
2
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3802 GROUP USER'S MANUAL
APPENDIX
3.10 Machine instructions
Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n 4C 3 ABS, X # OP n 3 ABS, Y IND ZP, IND # OP n 3 B2 4 IND, X IND, Y REL SP # OP n # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n
# OP n 6C 5
# OP n 2
# OP n
# OP n
NV * *
20 6
3
02 7
2
22 5
2
*
*
*
*
*
*
*
*
B5 4
2
AD 4
3 BD 5
3 B9 5
3
A1 6
2 B1 6
2
N
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
B6 4 B4 4 56 6
2 AE 4 AC 4 4E 6
3
BE 5
3
N
*
*
*
*
*
Z
*
2
3 BC 5
3
N
*
*
*
*
*
Z
*
2
3 5E 7
3
0
*
*
*
*
*
Z
C
62 15 2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
2
N
*
*
*
*
*
Z
*
3802 GROUP USER'S MANUAL
3-71
APPENDIX
3.10 Machine instructions
Addressing mode Symbol Function Details IMP OP n PHA M(S)  A SS-1 Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1. Saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1. Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer. Increments the contents of stack pointer by 1 and restores the processor status register from the memory at the address indicated by the stack pointer. Shifts the contents of the memory or accumulator to the left by one bit. The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit. Shifts the contents of the memory or accumulator to the right by one bit. The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit. Rotates the contents of memory to the right by 4 bits. 40 6 1 48 3 IMM # OP n 1 A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n #
PHP
M(S)  PS SS-1
08 3
1
PLA
SS+1 A  M(S)
68 4
1
PLP
SS+1 PS  M(S)
28 4
1
ROL
7 
0 C 
2A 2
1
26 5
2
ROR
7 C
0 
6A 2
1
66 5
2
RRF
7  SS+1 PS  M(S) SS+1 PCL  M(S) SS+1 PCH  M(S) SS+1 PCL  M(S) SS+1 PCH  M(S)
0 
82 8
2
RTI
Returns from an interrupt routine to the main routine.
RTS
Returns from a subroutine to the main routine.
60 6
1
SBC (Note 1) (Note 5)
When T = 0 AA-M-C When T = 1 M(X)  M(X) - M - C
Subtracts the contents of memory and complement of carry flag from the contents of accumulator. The results are stored into the accumulator. Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the address indicated by index register X. The results are stored into the memory of the address indicated by index register X. Sets the specified bit in the accumulator or memory to "1". Sets the contents of the carry flag to "1". 38 2 1
E9 2
2
E5 3
2
SEB
Ab or Mb  1 C1 D1 I1 T1
0B 2 + 2i
1
0F 5 + 2i
2
SEC
SED
Sets the contents of the decimal mode flag to "1". Sets the contents of the interrupt disable flag to "1". Sets the contents of the index X mode flag to "1". Disconnects the oscillator output from the XOUT pin.
F8 2
1
SEI
78 2
1
SET
32 2
1
SLW
C2 2
1
3-72
3802 GROUP USER'S MANUAL
APPENDIX
3.10 Machine instructions
Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n
# OP n
# OP n
# OP n
# OP n
NV * *
*
*
*
*
*
*
*
*
N
*
*
*
*
*
Z
*
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
*
*
*
*
*
Z
C
76 6
2
6E 6
3 7E 7
3
N
*
*
*
*
*
Z
C
*
*
*
*
*
*
*
*
(Value saved in stack)
*
*
*
*
*
*
*
*
F5 4
2
ED 4
3 FD 5
3 F9 5
3
E1 6
2 F1 6
2
NV
*
*
*
*
Z
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
*
*
*
*
1
*
*
*
*
*
*
*
*
1
*
*
*
*
1
*
*
*
*
*
*
*
*
*
*
*
*
*
3802 GROUP USER'S MANUAL
3-73
APPENDIX
3.10 Machine instructions
Addressing mode Symbol Function Details IMP OP n STA MA Stores the contents of accumulator in memory. IMM # OP n A # OP n BIT, A # OP n ZP # OP n 85 4 42 2 BIT, ZP # OP n 2 #
STP MX MY XA YA M = 0? XS AX SX AY
Stops the oscillator.
1
STX
Stores the contents of index register X in memory. Stores the contents of index register Y in memory. Transfers the contents of the accumulator to index register X. Transfers the contents of the accumulator to index register Y. Tests whether the contents of memory are "0" or not. Transfers the contents of the stack pointer to BA 2 index register X. Transfers the contents of index register X to the accumulator. Transfers the contents of index register X to the stack pointer. Transfers the contents of index register Y to the accumulator. Stops the internal clock. 8A 2 1 AA 2 1
86 4 84 4
2
STY
2
TAX
TAY
A8 2
1
TST
64 3
2
TSX
TXA
1
TXS
9A 2
1
TYA
98 2
1
WIT Notes 1 2 3 4 5
C2 2
1
: The number of cycles "n" is increased by 3 when T is 1. : The number of cycles "n" is increased by 2 when T is 1. : The number of cycles "n" is increased by 1 when T is 1. : The number of cycles "n" is increased by 2 when branching has occurred. : N, V, and Z flags are invalid in decimal operation mode.
3-74
3802 GROUP USER'S MANUAL
APPENDIX
3.10 Machine instructions
Addressing mode ZP, X OP n 95 5 ZP, Y # OP n 2 ABS # OP n 8D 5 ABS, X # OP n 3 9D 6 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7
Processor status register 6 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n 3 99 6
# OP n 3
# OP n 81 7
# OP n 2 91 7
# OP n 2
NV * *
*
*
*
*
*
*
*
*
96 5
2 8E 5
3
*
*
*
*
*
*
*
*
94 5
2
8C 5
3
*
*
*
*
*
*
*
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
N
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
Symbol IMP IMM A BIT, A ZP BIT, ZP ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N
Contents Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag + -
Symbol
Contents Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits. Contents of address indicated by zero page ADL 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes
V - V -  X Y S PC PS PCH PCL ADH ADL FF nn M M(X) M(S) M(ADH, ADL)
M(00, ADL) Ab Mb OP n #
3802 GROUP USER'S MANUAL
V
3-75
APPENDIX
3.11 SFR memory map
3.11 SFR memory map
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY)
PWM control register (PWMCON)
PWM prescaler (PREPWM) PWM register (PWM)
AD/DA control register (ADCON) A-D conversion register (AD) D-A1 conversion register (DA1) D-A2 conversion register (DA2)
Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON)
003816 003916 003A16 003B16 003C16 003D16 003E16
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2)
Serial I/O2 register (SIO2)
003F16
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3802 GROUP USER'S MANUAL
APPENDIX
3.12 Pin configuration
3.12 Pin configuration
PIN CONFIGURATION (TOP VIEW)
P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15
41 40 38 37 39 36 35 48
P37/RD P36/WR P35/SYNC P34/ P33/RESETOUT P32/ONW P31/DA2 P30/DA1 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63 /AN3
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
10 11 12 13 15 14 16 1 3 4 5 7 2 6 8 9
47
43 42
34 33
45 44
46
32 31 30 29 28 27 26
M38022M4-XXXFP
25 24 23 22 21 20 19 18 17
P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 VSS XOUT XIN P40/INT4 P41/INT0 RESET CNVSS P42/INT1
P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT2
Package type : 64P6N-A 64-pin plastic-molded QFP
3802 GROUP USER'S MANUAL
3-77
APPENDIX
3.12 Pin configuration
PIN CONFIGURATION (TOP VIEW)
VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT2 P42/INT1 CNVSS RESET P41/INT0 P40/INT4 XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P30/DA1 P31/DA2 P32/ONW P33/RESETOUT P34/ P35/SYNC P36/WR P37/RD P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7
Package type : 64P4B 64-pin shrink plastic-molded DIP
3-78
3802 GROUP USER'S MANUAL
M38022M4-XXXSP
MITSUBISHI SEMICONDUCTORS USER'S MANUAL 3802Group
Mar. First Edition 1996 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
(c)1996 MITSUBISHI ELECTRIC CORPORATION
User's Manual 3802 Group
H-EE417-A KI-9603 Printed in Japan (ROD) (c) 1996 MITSUBISHI ELECTRIC CORPORATION
New publication, effective Mar. 1996. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
3802 GROUP USER'S MANUAL
Revision Description Rev. date 980110
(1/1)