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M95256-D-RCS3TGK

M95256-D-RCS3TGK DataSheet STMicroelectronics 256 Kbit serial SPI bus EEPROM with high-speed clock

Kbit serial EEPROM with high-speed clock

STMicroelectronics

413.274 Kb

48 Pages

Maker Site:
http://www.st.com/

STMicroelectronics

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---Full Text Search Engine--- M95256-D-RCS3TGK STMicroelectronics
---Full Text Search Engine--- Kbit serial EEPROM with high-speed clock

M95256-MW6G_A M95256-D-MW6G_A M95256-MW6G_K M95256-D-MW6G_K
M95256-MW6TG_A M95256-D-MW6TG_A M95256-MW6TG_K M95256-D-MW6TG_K
M95256-MW3G_A M95256-D-MW3G_A M95256-MW3G_K M95256-D-MW3G_K
M95256-MW3TG_A M95256-D-MW3TG_A M95256-MW3TG_K M95256-D-MW3TG_K
M95256-MN3G_A M95256-D-MN3G_A M95256-MN3G_K M95256-D-MN3G_K
M95256-WMN6G_A M95256-D-WMN6G_A M95256-WMN6G_K M95256-D-WMN6G_K
M95256-MN3TG_A M95256-MN3TG_K M95256-MN6G_A M95256-DW3G_A
M95256-D-DW3G_A M95256-DW3G_K M95256-D-DW3G_K M95256-RCS3G_A
M95256-D-RCS3G_A M95256-RCS3G_K M95256-D-RCS3G_K M95256-D-RCS3TG_A
M95256-RCS3TG_K M95256-D-RCS3TG_K M95256-D-MN6G_A M95256-MN6G_K
M95256-D-MN6G_K M95256-D-CS3G_A M95256-D-CS3G_K M95256-D-CS3TG_A
M95256-D-CS3TG_K M95256-D-CS6G_A M95256-D-CS6G_K M95256-D-CS6TG_A
M95256-D-CS6TG_K M95256-D-DW3TG_A M95256-D-DW3TG_K M95256-D-DW6G_A
M95256-D-DW6G_K M95256-D-DW6TG_A M95256-D-DW6TG_K M95256-D-MN3TG_A
M95256-D-MN3TG_K M95256-D-MN6TG_A M95256-D-MN6TG_K M95256-RCS3TG_A

M95256-DR M95256 M95256-W M95256-R
256 Kbit serial SPI bus EEPROM with high-speed clock
Features
 
Compatible with the Serial Peripheral Interface (SPI) bus Memory array - 256 Kb (32 Kbytes) of EEPROM - Page size: 64 bytes Additional Write lockable Page (Identification page) Write - Byte Write within 5 ms - Page Write within 5 ms Write Protect: quarter, half or whole memory array High-speed clock frequency (20 MHz) Single supply voltage: 1.8 V to 5.5 V More than 1 Million Write cycles More than 40-year data retention Enhanced ESD Protection Packages - ECOPACK2(R) (RoHS compliant and Halogen-free) SO8 (MW) 200 mil width
SO8 (MN) 150 mil width
 
      
TSSOP8 (DW) 169 mil width
WLCSP (CS)
September 2010
Doc ID 12276 Rev 11
1/48
www.st.com 1
Contents
M95256-DR, M95256, M95256-W, M95256-R
Contents
1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8.1 3.8.2 3.8.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 4.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 5.2 5.3 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1 5.3.2 5.3.3 5.3.4 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 5.5 5.6
2/48
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R 5.6.1
Contents
ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . 22
5.7 5.8 5.9 5.10
Read Identification Page (available only in M95256-DR devices) . . . . . . 23 Write Identification Page (available only in M95256-DR devices) . . . . . . 24 Read Lock Status (available only in M95256-DR devices) . . . . . . . . . . . . 25 Lock ID (available only in M95256-DR devices) . . . . . . . . . . . . . . . . . . . . 25
6 7
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 9 10 11 12
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 12276 Rev 11
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List of tables
M95256-DR, M95256, M95256-W, M95256-R
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 M95256-R instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating conditions (M95256) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operating conditions (M95256-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operating conditions (M95256-R and M95256-DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC characteristics (M95256, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC characteristics (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DC characteristics (M95256-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC characteristics (M95256-R, M95256-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 33 AC characteristics (M95256, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AC characteristics, new M95256-W, device grade 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 AC characteristics (M95256-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC characteristics (M95256-DR, M95256-R device grade 6). . . . . . . . . . . . . . . . . . . . . . . 37 SO8N - 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 39 SO8 wide - 8 lead plastic small outline, 200 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TSSOP8 - 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 41 M95256-DR WLCSP, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . 42 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Available M95256x products (package, voltage range, temperature grade) . . . . . . . . . . . 44 Available M95256-DR products (package, voltage range, temperature grade) . . . . . . . . . 44 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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M95256-DR, M95256, M95256-W, M95256-R
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SO8N - 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 39 SO8 wide - 8 lead plastic small outline, 200 mils body width, package outline . . . . . . . . . 40 TSSOP8 - 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 41 M95256-DR WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Description
M95256-DR, M95256, M95256-W, M95256-R
1
Description
The M95256, M95256-W, M95256-R and M95256-DR are electrically erasable programmable memory (EEPROM) devices. They are accessed by a high speed SPIcompatible bus. Their memory array is organized as 32768 x 8 bits. The M95256-DR also offers an additional page, named the Identification Page (64 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification Page offers flexibility in the application board production line, as the Identification Page can be used to store unique identification parameters and/or parameters specific to the production line. The device is accessed by a simple serial interface that is SPI-compatible. Figure 1. Logic diagram
VCC
D C S W HOLD M95256
Q
VSS
AI12361
The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD). Figure 2. 8-pin package connections
M95256 S Q W VSS 1 2 3 4 8 7 6 5 VCC HOLD C D
AI12362
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
Caution:
As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by ST Microelectronics must never be exposed to UV light.
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R Figure 3.
Description
WLCSP connections (top view, marking side, with balls on the underside)
VCC S HOLD D C
Q
W
VSS
ai14707
Table 1.
Signal names
Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Input Input Output Input Input Input Direction
Signal name C D Q S W HOLD VCC VSS
Doc ID 12276 Rev 11
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Memory organization
M95256-DR, M95256, M95256-W, M95256-R
2
Memory organization
The memory is organized as shown in Figure 4. Figure 4.
HOLD W S C D Q Control Logic
Block diagram
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register
Size of the Read only EEPROM area
Y Decoder
1 Page
X Decoder
AI01272C
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
Signal description
3
Signal description
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
3.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
3.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
3.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data output (Q) changes after the falling edge of Serial Clock (C).
3.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
3.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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Signal description
M95256-DR, M95256, M95256-W, M95256-R
3.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions.
3.7
VSS ground
VSS is the reference for the VCC supply voltage.
3.8
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9, Table 10). This voltage must remain stable and valid until the end of the transmission of the instructionand, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
3.8.1
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal Reset threshold voltage (this threshold is defined in DC tables as VRES). (this threshold is lower than the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10). When VCC passes over the POR threshold, the device is reset and in the following state:
  
in Standby Power mode, deselected (note that a further instruction must be preceded by a falling edge on Chip Select (S) to be executed), Status Register value: - - - the Write Enable Latch (WEL) is reset to 0, Write In Progress (WIP) is reset to 0, The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode, however, the device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8, Table 9 and Table 10).
3.8.2
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
Operating features
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 17). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been High, prior to going Low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10 and the rise time must not vary faster than 1 V/s.
3.8.3
Power-down
During Power-down (continuous decrease of VCC supply voltage below the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10), the device must be:
 
deselected (Chip Select S should be allowed to follow the voltage applied on VCC) in Standby Power mode (there should not be an internal Write cycle in progress).
4
4.1
Operating features
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as Serial Clock (C) already being low (as shown in Figure 5). The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as Serial Clock (C) already being low. Figure 5 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low.
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Operating features Figure 5. Hold condition activation
M95256-DR, M95256, M95256-W, M95256-R
C
HOLD
Hold Condition
Hold Condition
AI02029D
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M95256-DR, M95256, M95256-W, M95256-R
Operating features
4.2
Status Register
Figure 4 shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. For a detailed description of the Status Register bits, see Section 5.3: Read Status Register (RDSR).
4.3
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms:
 
Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write (WRITE) instruction completion
 
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only. The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:

The `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). The `next rising edge of Serial Clock (C)' might (or might not) be the next bus transaction for some other device on the SPI bus. Write-protected block size
Protected array addresse Protected block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory M95256, M95256-W, M95256-R none 6000h - 7FFFh 4000h - 7FFFh 0000h - 7FFFh

Table 2.
Status Register bits
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Instructions
M95256-DR, M95256, M95256-W, M95256-R
5
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3. Instruction set
Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Instruction WREN WRDI RDSR WRSR READ WRITE
Table 4.
M95256-R instruction set
Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 1000 0011(1) 1000 0010(1) 1000 0011(2) 1000 0010(2)
Instruction WREN WRDI RDSR WRSR READ WRITE
Read Identification Reads the page dedicated to identification. Page Write Identification Writes the page dedicated to identification. Page Read Lock Status Lock ID Reads the lock status of the Identification Page. Locks the Identification page in read-only mode.
1. Address bit A10 must be 0, all other address bits are Don't Care. 2. Address bit A10 must be 1, all other address bits are Don't Care.
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M95256-DR, M95256, M95256-W, M95256-R
Instructions
5.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. Figure 6. Write Enable (WREN) sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
5.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
   
Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion Write Disable (WRDI) sequence
S 0 C Instruction D High Impedance Q
AI03750D
Figure 7.
1
2
3
4
5
6
7
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Instructions
M95256-DR, M95256, M95256-W, M95256-R
5.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 8. The status and control bits of the Status Register are as follows:
5.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
5.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted.
5.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 5) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
5.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5.
b7 SRWD 0 0 0 BP1 BP0 WEL
Status Register format
b0 WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit
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M95256-DR, M95256, M95256-W, M95256-R Figure 8.
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 Status Register Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instructions
Read Status Register (RDSR) sequence
0
7
AI02031E
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Instructions
M95256-DR, M95256, M95256-W, M95256-R
5.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must have been previously executed. The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, the data byte on Serial Data Input (D) and the Chip Select (S) driven High. Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed. The instruction sequence is shown in Figure 9. Driving the Select (S) High at a byte boundary of the input data triggers the self timed Write cycle, and continues for a period tW (as specified in Table 17, Table 18, Table 19 and Table 20). While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the selftimed Write cycle tW, and is 0 when the Write cycle is completed. The WEL bit (Write Enable Latch) is also reset when the Write cycle tW is completed. The Write Status Register (WRSR) instruction allows the user to change the values of the BP1, BP0 bits and the SRWD bit:
 
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as read only, as defined in Table 2. The SRWD bit (Status Register Write Disable bit), in accordance with the signal read on the Write Protect pin (W), allows the user to set or reset the Write protection mode of the Status Register itself, as defined in Table 6 When in Write Protected mode, the Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the tW Write cycle. The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b4, b1, b0 of the Status Register. Bits b6, b5, b4 are always read as 0. Table 6.
W signal 1 0
Protection modes
SRWD bit 0 0 Mode Write protection of the Status Register Memory content Protected area(1) Unprotected area(1)
1
1
Status Register is Writable (if the WREN Software instruction has set the Protected WEL bit) (SPM) The values in the BP1 and BP0 bits can be changed
Write-protected
Ready to accept Write instructions
0
1
Status Register is Hardware write Hardware protected Protected Write-protected (HPM) The values in the BP1 and BP0 bits cannot be changed
Ready to accept Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6.
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M95256-DR, M95256, M95256-W, M95256-R The protection features of the device are summarized in Table 6.
Instructions
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction), regardless of the logic level applied on the Write Protect (W) input pin. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W) input pin:
 
If Write Protect (W) input pin is driven high, it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction. If Write Protect (W) input pin is driven low, it is not possible to write to the Status Register even if the WEL bit has previously been set by a WREN instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
 
either by setting the SRWD bit after driving Write Protect (W) input pin low, or by driving Write Protect (W) input pin low after setting the SRWD bit.
Once entered in the Hardware Protected mode (HPM), the only way to exit the HPM mode is to pull high the Write Protect (W) input pin. If Write Protect (W) input pin is permanently tied high, the Hardware Protected mode (HPM) can never be activated, and only the Software Protected mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. Figure 9. Write Status Register (WRSR) sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
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Instructions
M95256-DR, M95256, M95256-W, M95256-R
5.5
Read from Memory Array (READ)
As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data output (Q). If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 10. Read from Memory Array (READ) sequence
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI01793D
1. The most significant address bit (b15) is Don't Care.
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Instructions
5.6
Write to Memory Array (WRITE)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in, on Serial Data input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle, triggered by the rising edge of Chip Select (S), continues for a period tWC (as specified in Table 17, Table 18, Table 19 and Table 20.), at the end of which the Write in Progress (WIP) bit is reset to 0. In the case of Figure 11, Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. If, though, Chip Select (S) continues to be driven low, as shown in Figure 12, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 64 bytes). The instruction is not accepted, and is not executed, under the following conditions:
   
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a Write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Note:
The self-timed Write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as "0" and a programmed bit is read as "1". Figure 11. Byte Write (WRITE) sequence
S 0 C Instruction 16-Bit Address Data Byte 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
AI01795D
1. The most significant address bit (b15) is Don't Care.
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Instructions Figure 12. Page Write (WRITE) sequence
S 0 C Instruction 1 2 3 4 5 6 7 8
M95256-DR, M95256, M95256-W, M95256-R
9 10
20 21 22 23 24 25 26 27 28 29 30 31
16-Bit Address
Data Byte 1
D
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 Data Byte 3 Data Byte N
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
AI01796D
1. The most significant address bit (b15) is Don't Care.
5.6.1
ECC (error correction code) and Write cycling
The M95256 and M95256-D devices offer an ECC (error correction code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes making up the word. It is therefore recommended to write data in words (4 bytes) in order to optimize the number of Write cycles. The M95256 and M95256-D devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device in multiples of 4-byte words.
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M95256-DR, M95256, M95256-W, M95256-R
Instructions
5.7
Read Identification Page (available only in M95256-DR devices)
The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D). Address bit A10 must be 0, address bits [A17:A11] and [A9:A8] are Don't Care, and the data byte pointed to by [A7:A0] is shifted out on Serial Data output (Q). If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the ID page from location 24d, the number of bytes should be less than or equal to 40d, as the ID page boundary is 64 bytes). The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 13. Read Identification Page sequence
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Instructions
M95256-DR, M95256, M95256-W, M95256-R
5.8
Write Identification Page (available only in M95256-DR devices)
The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Table 4), the Chip Select signal (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in on Serial Data input (D). Address bit A10 must be 0, address bits [A23:A11] and [A9:A8] are Don't Care, the [A7:A0] address bits define the byte address inside the identification page. The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed write cycle triggered by the rising edge of Chip Select (S) continues for a period tW (as specified in Table 20), at the end of which the Write in Progress (WIP) bit is reset to 0. In the case of Figure 14, Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. However, if Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 64 bytes). The instruction is not accepted, and is not executed, under the following conditions:
    
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction) if Status register bits (BP1, BP0) = (1, 1) if a write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that was latched in) if the Identification page is locked by the Lock Status bit
Figure 14. Write Identification Page sequence
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Instructions
5.9
Read Lock Status (available only in M95256-DR devices)
The Read Lock Status instruction (see Table 4) allows to check if the Identification Page is locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q). It is at `1' when the lock is active and at `0' when the lock is not active. If Chip Select (S) continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is shown in Figure 15.
Figure 15. Read Lock Status sequence
5.10
Lock ID (available only in M95256-DR devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data input (D), and driving Chip Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Lock ID instruction is not executed. Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration is tW (specified in Table 20). The instruction sequence is shown in Figure 16.
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Instructions
M95256-DR, M95256, M95256-W, M95256-R
The instruction is not accepted, and so not executed, under the following conditions:
    
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction) if Status register bits (BP1,BP0) = (1,1) if a write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that was latched in) if the Identification page is locked by the Lock Status bit
Figure 16. Lock ID sequence
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Delivery state
6
Delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
7
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 17 shows an example of three memory devices connected to an MCU, on an SPI bus. Only one memory device is selected at a time, so only one memory device drives the Serial Data output (Q) line at a time, the other memory devices are high impedance. Figure 17. Bus master and memory devices on the SPI bus
VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD Bus Master (ST6, ST7, ST9, ST10, Others) R CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI Memory Device VCC VSS R SPI Memory Device CQD VCC VSS R SPI Memory Device CQD VCC VSS
AI12304b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
The pull-up resistor R (represented in Figure 17) ensures that a device is not selected if the bus master leaves the S line in the high-impedance state. In applications where the bus master might enter a state where all SPI bus inputs/outputs would be in high impedance at the same time (for example, if the bus master is reset during
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Connecting to the SPI bus
M95256-DR, M95256, M95256-W, M95256-R
the transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high): this ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 k.
7.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
 
CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 18, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
 
C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
Figure 18. SPI modes supported
CPOL CPHA C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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Maximum rating
8
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7.
Symbol
Absolute maximum ratings
Parameter Ambient temperature with power applied Min. -40 -65 see note -0.50 -0.50 -5 -0.50 model)(2) -4000 Max. 130 150
(1)
Unit C C C V V mA mA V V
TSTG TLEAD VO VI IOL IOH VCC VESD
Storage temperature Lead temperature during soldering Output voltage Input voltage DC output current (Q = 0) DC output current (Q = 1) Supply voltage Electrostatic discharge voltage (human body
VCC+0.6 6.5 5 6.5 4000
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100pF, R1=1500 , R2=500 )
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DC and AC parameters
M95256-DR, M95256, M95256-W, M95256-R
9
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8.
Symbol VCC TA Supply voltage Ambient operating temperature (device grade 3)
Operating conditions (M95256)
Parameter Min. 4.5 -40 Max. 5.5 125 Unit V C
Table 9.
Symbol VCC TA
Operating conditions (M95256-W)
Parameter Supply voltage Ambient operating temperature (device grade 6) Ambient operating temperature (device grade 3) Min. 2.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 10.
Symbol VCC TA
Operating conditions (M95256-R and M95256-DR)
Parameter Supply voltage Ambient operating temperature Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 11.
Symbol CL
AC measurement conditions(1)
Parameter Load capacitance Input rise and fall times Input pulse voltages Input and output timing reference voltages Min. Max. Unit pF ns V V
30 or 100(2) 25 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
1. Output Hi-Z is defined as the point where data out is no longer driven. 2. 100 pF when the clock frequency fC is less than 10 MHz, 30 pF when the clock frequency fC is equal to or greater than 10 MHz.
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R Figure 19. AC measurement I/O waveform
Input Levels 0.8VCC
DC and AC parameters
Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 12.
Symbol COUT CIN
Capacitance(1)
Parameter Output capacitance (Q) Input capacitance (D) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V VIN = 0 V Max. 8 8 6 Unit pF pF pF
1. Sampled only, not 100% tested.
Table 13.
Symbol ILI ILO ICC ICC1 VIL VIH VOL
(1) (1)
DC characteristics (M95256, device grade 3)
Parameter Input leakage current Output leakage current Supply current Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC Test condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open S = VCC, VCC = 5 V, VIN = VSS or VCC -0.45 0.7 VCC Min. Max. 2 2 4 5 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V
VOH
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
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DC and AC parameters Table 14.
Symbol ILI ILO
M95256-DR, M95256, M95256-W, M95256-R DC characteristics (M95256-W, device grade 6)
Parameter Test condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC VCC= 2.5 V, C = 0.1VCC/0.9VCC at 5 MHz, Q = open VCC= 2.5 V, C = 0.1VCC/0.9VCC at 10 MHz, Q = open Min. Max. 2 2 3 4(1) 5 5(2) 5 5(4) 5(5) -0.45 0.7 VCC VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA VCC = 2.5 V and IOH = -0.4 mA or 0.8 VCC VCC = 5 V and IOH = -2 mA 0.3 VCC VCC+1 0.4 Unit A A mA mA mA mA mA A A V V V V
Input leakage current Output leakage current
ICC
Supply current (Read) VCC= 5.5 V, C = 0.1VCC/0.9VCC at 5 MHz, Q = open VCC= 5.5 V, C = 0.1VCC/0.9VCC at 20 MHz, Q = open
ICC0(3)
Supply current (Write)
During tW, S = VCC, 2.5 V < VCC < 5.5 V S = VCC, VCC = 5.5 V, VIN = VSS or VCC, S = VCC, VCC = 2.5 V, VIN = VSS or VCC,
ICC1
Supply current (Standby Power mode)
VIL VIH VOL VOH
Input low voltage Input high voltage Output low voltage Output high voltage
1. Preliminary data: 2mA with the new product identified with process letter K. 2. For new product identified with process letter K (preliminary data) 3. Characterized value, not tested in production. 4. 3 A with the new product identified with process letter K (Preliminary data) 5. 2 A with the new product identified with process letter K (Preliminary data)
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R Table 15.
Symbol ILI ILO ICC ICC0(1) ICC1 VIL VIH VOL VOH
DC and AC parameters
DC characteristics (M95256-W, device grade 3)
Parameter Input leakage current Output leakage current Supply current (Read) Supply current (Write) Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage IOL = 1.5 mA, VCC = 2.5 V IOH = -0.4 mA, VCC = 2.5 V 0.8 VCC Test condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open During tW, S = VCC, 2.5 V < VCC < 5.5 V S = VCC, VIN = VSS or VCC 2.5 V < VCC < 5.5 V, -0.45 0.7 VCC Min. Max. 2 2 3 6 5 0.3 VCC VCC+1 0.4 Unit A A mA mA A V V V V
1. Characterized value, not tested in production.
Table 16.
Symbol ILI ILO ICC ICC0(5) ICC1 VIL VIH VOL VOH
2.
DC characteristics (M95256-R, M95256-DR, device grade 6)(1)
Parameter Input leakage current Output leakage current Supply current (Read) Supply current (Write) Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage Test condition(2) VIN = VSS or VCC S = VCC, VOUT = VSS or VCC VCC = 1.8 V, C = 0.1VCC/0.9VCC at 2 MHz, Q = open VCC = 1.8 V, C = 0.1VCC/0.9VCC at 5 MHz, Q = open VCC = 1.8 V, during tW, S = VCC VCC = 1.8 V, S = VCC, VIN = VSS or VCC 1.8 V  VCC < 2.5 V 1.8 V  VCC < 2.5 V IOL = 0.15 mA, VCC = 1.8 V IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC -0.45 0.75 VCC Min Max 2 2 1 (3) 2(4) 3 3 0.25 VCC VCC+1 0.3 mA mA A V V V V Unit A A
1. New product identified with process letter K. If the application uses the M95256-R, M95256-DR device with 2.5 V < VCC < 5.5 V and -40 C < TA < +85 C, please refer to Table 14: DC characteristics (M95256-W, device grade 6) instead of the above table.
3. 2 mA for the new product identified with the process letter K (Preliminary data). 4. Only the new product identified with the process letter K can run at 5 MHz (Preliminary data) 5. Characterized value, not tested in production.
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DC and AC parameters Table 17.
M95256-DR, M95256, M95256-W, M95256-R AC characteristics (M95256, device grade 3)
Test conditions specified in Table 11: AC measurement conditions and Table 8: Operating conditions (M95256) Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH
(1)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency S active setup time
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCL (1) tCLCH tCHCL
(2) (2)
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tCLQV tCLQX tQLQH (2) tQHQL
(2)
tHHQV tHLQZ tW
(2)
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not tested in production.
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M95256-DR, M95256, M95256-W, M95256-R Table 18. AC characteristics, new M95256-W, device grade 6
Test conditions: VCC = 2.5 to 5.5 V, TA = -40 to 85 C Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH (1) tCL (1) tCLCH (2) tCHCL (2) tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ (2) tCLQV tCLQX tQLQH (2) tQHQL (2) tHHQV tHLQZ (2) tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH Alt. fSCK tCSS1 tCSS2 tCS tCSH Parameter Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time 0 50 50 50 100 5 20 30 70 40 0 0 100 60 0 CL = 100 pF
DC and AC parameters
New products (process K, preliminary information) CL = 30 pF Unit Max. 20 MHz ns ns ns ns ns ns ns 2 2 5 10 15 15 0 0 40 40 0 40 40 40 40 5 20 20 20 20 5 20 20 s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Min. D.C. 30 30 40 30 30 45 45
Max. 10
Min. D.C. 15 15 20 15 15 20 20
1 1 10 10 30 30 0 0
2 2
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not tested in production.
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DC and AC parameters Table 19.
M95256-DR, M95256, M95256-W, M95256-R AC characteristics (M95256-W, device grade 3)
Test conditions specified in Table 11: AC measurement conditions and Table 9: Operating conditions (M95256-W) Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH
(1)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency S active setup time
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCL (1) tCLCH tCHCL
(2) (2)
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tCLQV tCLQX tQLQH (2) tQHQL
(2)
tHHQV tHLQZ tW
(2)
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not tested in production.
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M95256-DR, M95256, M95256-W, M95256-R Table 20. AC characteristics (M95256-DR, M95256-R device grade 6)
Test conditions: VCC = 1.8 to 5.5 V, TA = -40 to 85 C Min. Symbol Alt. Parameter Max.
DC and AC parameters
Min.
Max.
New
Current(1) products D.C. 200 200 200 200 200 200 200 1 1 40 50 140 90 0 0 250 150 0 100 100 100 250 5 0 20 20 80 80 5 20 20 60 60 0 0 80 80 2 products(2) (Preliminary information) D.C. 60 60 90 60 60 80 80 2 2 5
Unit
fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH tCL
(3) (3)
fSCK tCSS1 tCSS2 tCS tCSH
Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time
MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH (4) tCHCL
(4)
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ (4) tCLQV tCLQX tQLQH
(4)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tQHQL (4) tHHQV tHLQZ tW
(4)
1. Current products are identified by process letters "AB". 2. New products are identified by process letter K. For these new products, the test flow guarantees the AC parameter values defined in this table (when VCC = 1.8 V) and the AC parameter values defined in Table 18 (when VCC= 2.5 V or VCC= 5.0 V). The M95256-DR is available as only "new product" type. 3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 4. Value guaranteed by characterization, not 100% tested in production.
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DC and AC parameters Figure 20. Serial input timing
M95256-DR, M95256, M95256-W, M95256-R
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
Figure 21. Hold timing
S tHLCH tCLHL C tCLHH tHLQZ Q tHHQV tHHCH
HOLD
AI01448c
Figure 22. Output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449e
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M95256-DR, M95256, M95256-W, M95256-R
Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers the M95256 in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 23. SO8N - 8 lead plastic small outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 21.
Symbol
SO8N - 8 lead plastic small outline, 150 mils body width, package data
millimeters Typ Min Max 1.75 0.1 1.25 0.28 0.17 0.48 0.23 0.1 4.9 6 3.9 1.27 4.8 5.8 3.8 0.25 0 0.4 1.04 5 6.2 4 0.5 8 1.27 0.0409 0.1929 0.2362 0.1535 0.05 0.189 0.2283 0.1496 0.0098 0 0.0157 0.25 0.0039 0.0492 0.011 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 0.0197 8 0.05 Typ inches(1) Min Max 0.0689 0.0098
A A1 A2 b c ccc D E E1 e h k L L1
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M95256-DR, M95256, M95256-W, M95256-R
Figure 24. SO8 wide - 8 lead plastic small outline, 200 mils body width, package outline
A2 b e D
A c CP
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 22.
SO8 wide - 8 lead plastic small outline, 200 mils body width, package mechanical data
millimeters inches(1) Max 2.5 0 1.51 0.4 0.2 0.35 0.1 0.25 2 0.51 0.35 0.1 6.05 5.02 7.62 1.27 0 0.5 8 6.22 8.89 10 0.8 0.05 0.1976 0.3 0 0.0197 8 0.0157 0.0079 0 0.0594 0.0138 0.0039 Typ Min Max 0.0984 0.0098 0.0787 0.0201 0.0138 0.0039 0.2382 0.2449 0.35 10 0.0315
Symbol Typ A A1 A2 b c CP D E E1 e k L N Min
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
Package mechanical data
Figure 25. TSSOP8 - 8 lead thin shrink small outline, package outline
D
8
5
c
E1 E
1
4

A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale.
Table 23.
Symbol
TSSOP8 - 8 lead thin shrink small outline, package mechanical data
millimeters Typ Min Max 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0 8 8 2.900 - 6.200 4.300 0.450 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ inches(1) Min Max 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295
A A1 A2 b c CP D e E E1 L L1  N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M95256-DR, M95256, M95256-W, M95256-R
Figure 26. M95256-DR WLCSP, 0.5 mm pitch, package outline
Orientation reference 3 D 2 1
e2 e E G B
A B C D E
F
e3 e1 A2 A1 A
1. Drawing is not to scale.
Table 24.
Symbol
M95256-DR WLCSP, 0.5 mm pitch, package mechanical data
Millimeters Inches(1) Max 0.65 0.27 0.380 Typ 0.0236 0.0096 0.0140 Min 0.0217 0.0087 0.0130 O 0.0122 1.99 1.805 0.0776 0.0703 0.0197 0.0341 0.0098 0.0170 0.502 0.342 8 0.602 0.442 0.0217 0.0154 0.0198 0.0135 8 0.0237 0.0174 0.0768 0.0695 0.0783 0.0711 Max 0.0256 0.0106 0.0150
Typ
A A1 A2 B D E e e1 e2 e3 F G N(2) 1.97 1.785 0.5 0.866 0.25 0.433 0.552 0.392 0.60 0.245 0.355
Min
0.55 0.22 0.330 O 0.311 1.95 1.765
1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. N is the total number of terminals.
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
Part numbering
11
Part numbering
Table 25.
Example: Device type M95 = SPI serial access EEPROM Device function 256 = 256 Kbit 256-D = 256 Kbit plus Identification page Operating voltage blank = VCC = 4.5 to 5.5 V W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V Package MN = SO8 (150 mils width) MW = SO8 (200 mils width) DW = TSSOP8 (169 mils width) CS = WLCSP Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Device tested with High Reliability Certified Flow(1) Automotive temperature range (-40 to 125 C) Option blank = Standard packing T = Tape and reel packing Plating technology P or G = ECOPACK(R) (RoHs compliant) Process A or AB = F8L(2) K= F8H
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Used only for device grade 3 and WLCSP packages.
Ordering information scheme
M95256 - W MN 6 T P /A
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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Part numbering
M95256-DR, M95256, M95256-W, M95256-R
The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Table 26. Available M95256x products (package, voltage range, temperature grade)
M95256 (4.5 V to 5.5 V) Range 3 M95256-W (2.5 V to 5.5 V) Range 6, Range 3 Range 6 Range 6, Range 3 M95256-R (1.8 V to 5.5 V) Range 6 Range 6 Range 6
Package SO8N (MN) SO8W (MW) TSSOP (DW) WLCSP
Table 27.
Available M95256-DR products (package, voltage range, temperature grade)
Package M95256-DR 1.8 V to 5.5 V Range 6 Range 6
SO8 (MN) TSSOP (DW)
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M95256-DR, M95256, M95256-W, M95256-R
Revision history
12
Revision history
Table 28.
Date 17-Nov-1999 07-Feb-2000 22-Feb-2000 15-Mar-2000 29-Jan-2001
Document revision history
Revision 2.1 2.2 2.3 2.4 2.5 Changes New -V voltage range added (including the tables for DC characteristics, AC characteristics, and ordering information). New -V voltage range extended to M95256 (including AC characteristics, and ordering information). tCLCH and tCHCL, for the M95xxx-V, changed from 1s to 100ns -V voltage range changed to 2.7-3.6V Lead Soldering Temperature in the Absolute Maximum Ratings table amended Illustrations and Package Mechanical data updated Correction to header of Table 12B TSSOP14 Illustrations and Package Mechanical data updated Document promoted from Preliminary Data to Full Data Sheet Announcement made of planned upgrade to 10 MHz clock for the 5V, -40 to 85C, range. M95128 split off to its own datasheet. Data added for new and forthcoming products, including availability of the SO8 narrow package. Omission of SO8 narrow package mechanical data remedied -V voltage range removed Table of contents, and Pb-free options added. -S voltage range extended to -R. VIL(min) improved to -0.45V Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified M95128 datasheet merged back in. Product List summary table added. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX corrected to tHHQV. 10MHz product becomes standard
12-Jun-2001
2.6
08-Feb-2002 09-Aug-2002 24-Feb-2003 26-Jun-2003 21-Nov-2003
2.7 2.8 2.9 2.10 3.0
17-Mar-2004
4.0
21-Oct-2004
5.0
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Revision history Table 28.
Date
M95256-DR, M95256, M95256-W, M95256-R Document revision history (continued)
Revision Changes M95128 part numbers removed from document. PDIP8 package removed. Delivery state paragraph added. Section 3.8: Operating supply voltage (VCC) added and information removed below Section 4: Operating features. Power up state removed below Section 6: Delivery state. Figure 18: SPI modes supported modified and Note 2 added. Note 1 added to Table 8. ICC1 specified over the whole VCC range and ICC0 added in Table 14, Table 15 and Table 16. ICC specified over the whole VCC range in Table 14. Table 17: AC Characteristics (M95256, Device Grade 6) added. tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively. Figure 21: Hold timing modified. Process added to Table 25: Ordering information scheme. Note 1 added to Table 25. Note 1 removed from Table 20: AC characteristics (M95256-DR, M95256R device grade 6). TA added to Table 7: Absolute maximum ratings. Order of sections modified. M95256 with device grade 6 temperature range removed. Section 3.7: VSS ground added, Section 3.8: Operating supply voltage (VCC) modified. Small text changes. Section 5.4: Write Status Register (WRSR), Section 5.5: Read from Memory Array (READ) and Section 6: Delivery state updated. Note 2 below Figure 17: Bus master and memory devices on the SPI bus removed, replaced by explanatory paragraph. TLEAD added to Table 7: Absolute maximum ratings. Test conditions modified for ICC0 and ICC1, and VIH min modified in Table 17: AC characteristics (M95256, device grade 3). tW modified and "preliminary data" note removed in Table 20: AC characteristics (M95256-DR, M95256-R device grade 6). Blank option removed below Plating technology, process A modified and process V removed in Table 25: Ordering information scheme. Table 26: Available M95256x products (package, voltage range, temperature grade) added. SO8N and SO8W package specifications updated (see Section 10: Package mechanical data). Package mechanical data: inches calculated from mm and rounded to 3 decimal digits. Section 3.8: Operating supply voltage (VCC) modified. Small text changes. Frequency corrected on page 1. VIL and VIH modified in Table 16: DC characteristics (M95256-R, M95256DR, device grade 6). AB Process added to Table 25: Ordering information scheme. WLCSP package added (see Figure 3: WLCSP connections (top view, marking side, with balls on the underside) and Section 10: Package mechanical data).
13-Apr-2006
6
15-Oct-2007
7
27-Mar-2008
8
15-Jul-2008
9
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R Table 28.
Date
Revision history
Document revision history (continued)
Revision Changes M95256-DR part number added. Updated Section 3.8: Operating supply voltage (VCC) Updated Section 4.3: Data protection and protocol control Updated Section 5.4: Write Status Register (WRSR) Added note in Section 5.6: Write to Memory Array (WRITE) Updated Table 7: Absolute maximum ratings Added Table 20: AC characteristics (M95256-DR, M95256-R device grade 6) Updated Table 20: AC characteristics (M95256-DR, M95256-R device grade 6) Updated Section 1: Description. Updated Section 5.7: Read Identification Page (available only in M95256DR devices). Updated Section 5.8: Write Identification Page (available only in M95256DR devices). Updated Section 5.9: Read Lock Status (available only in M95256-DR devices).
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M95256-DR, M95256, M95256-W, M95256-R
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