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M95512-RCS3TGAB

M95512-RCS3TGAB DataSheet STMicroelectronics 512 Kbit serial SPI bus EEPROM with high-speed clock

Kbit serial EEPROM with high-speed clock

STMicroelectronics

404.216 Kb

48 Pages

Maker Site:
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STMicroelectronics

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M95512-WCS3TP_AB M95512-WCS3TP_K M95512-RMB6G_AB M95512-RMB6G_K
M95512-RMB6P_AB M95512-RMB6P_K M95512-RMB6TG_AB M95512-RMB6TG_K
M95512-RMB6TP_AB M95512-RMB6TP_K M95512-RDW6G_AB M95512-RDW6G_K
M95512-RDW6P_AB M95512-RDW6P_K M95512-RDW6TG_AB M95512-RDW6TG_K
M95512-WDW6G_AB M95512-WDW6G_K M95512-WDW6P_AB M95512-WDW6P_K
M95512-WDW6TG_AB M95512-WDW6TG_K M95512-WMN3P_AB M95512-WMN3P_K
M95512-WMN3TG_AB M95512-WMN3TG_K M95512-WMN3TP_AB M95512-WMN3TP_K
M95512-WMB6G_AB M95512-WMB6G_K M95512-WMB6P_AB M95512-WMB6P_K
M95512-WMB6TG_AB M95512-WMB6TG_K M95512-WMB6TP_AB M95512-WMB6TP_K
M95512-WMN6G_AB M95512-WMN6G_K M95512-WMN6P_AB M95512-WMN6P_K
M95512-WMN6TG_AB M95512-WMN6TG_K M95512-WMN6TP_AB M95512-RMN6G_AB
M95512-RMN6G_K M95512-RMN6P_AB M95512-RMN6P_K M95512-RMN6TG_AB
M95512-RMN6TG_K M95512-RMN6TP_AB M95512-RMN6TP_K M95512-D-WMN6G_AB
M95512-D-WMN6G_K M95512-D-WMN3P_AB M95512-D-RMN3P_AB M95512-RCS3G_AB
M95512-D-RCS3G_AB M95512-RCS3G_K M95512-D-RCS3G_K M95512-RCS3P_AB
M95512-D-RCS3P_AB M95512-RCS3P_K M95512-D-RCS3P_K M95512-RCS3TG_AB
M95512-RCS3TG_K M95512-D-RCS3TG_K M95512-RCS3TP_AB M95512-D-RCS3TP_AB
M95512-RCS3TP_K M95512-D-RCS3TP_K

M95512-DR M95512-R M95512-W
512 Kbit serial SPI bus EEPROM with high-speed clock
Features
 
Compatible with the Serial Peripheral Interface (SPI) bus Memory array - 512 Kb (64 Kbytes) of EEPROM - Page size: 128 bytes Additional Write lockable Page (Identification page) Write - Byte Write within 5 ms - Page Write within 5 ms Write Protect: quarter, half or whole memory array High-speed clock frequency (20 MHz) Single supply voltage: 1.8 V to 5.5 V More than 1 Million Write cycles More than 40-year data retention Enhanced ESD Protection Packages - ECOPACK2(R) (RoHS compliant and Halogen-free)
WLCSP (CS) TSSOP8 (DW) 169 mils width SO8 (MN) 150 mils width
 
      
UFDFPN8 (MB) 2 x 3 mm (MLP)
September 2010
Doc ID 11124 Rev 13
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www.st.com 1
Contents
M95512-W, M95512-R
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1 4.1.2 4.1.3 4.1.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 4.3 4.4 4.5
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 6.2 6.3 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M95512-W, M95512-R 6.3.2 6.3.3 6.3.4
Contents WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 6.5 6.6 6.7 6.8 6.9 6.10
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Identification Page (available only in M95512-DR devices) . . . . . . 25 Write Identification Page (available only in M95512-DR devices) . . . . . . 26 Read Lock Status (available only in M95512-DR devices) . . . . . . . . . . . . 27 Lock ID (available only in M95512-DR devices) . . . . . . . . . . . . . . . . . . . . 27
7 8
ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 29 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 8.2 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 10 11 12 13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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List of tables
M95512-W, M95512-R
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 M95512-W and M95512-R instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M95512-DR instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operating conditions (M95512-W device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating conditions (M95512-W device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating conditions (M95512-R and M95512-DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DC characteristics (current M95512-W products). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DC characteristics (new M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC characteristics (current and new M95512-R and M95512-DR products) . . . . . . . . . . . 33 AC characteristics (current M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AC characteristics (New M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 AC characteristics (current and new M95512-R and M95512-DR products) . . . . . . . . . . . 36 SO8N - 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TSSOP8 - 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 40 UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 .mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 WLCSP-R - 8-bump wafer-length chip-scale package mechanical data . . . . . . . . . . . . . . 42 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Available M95512 products (package, voltage range, temperature grade) . . . . . . . . . . . . 44 Available M95512-DR products (package, voltage range, temperature grade) . . . . . . . . . 44 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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M95512-W, M95512-R
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO8, TSSOP8 and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SO8N - 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 39 TSSOP8 - 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 40 UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 WLCSP-R - 8-bump wafer-length chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . 42
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Description
M95512-W, M95512-R
1
Description
The M95512-W, M95512-R and M95512-DR are electrically erasable programmable memory (EEPROM) devices accessed by a high-speed SPI-compatible bus. In the rest of the document these devices are referred to as M95512, unless otherwise specified. The M95512-DR also offers an additional page, named the Identification Page (128 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification Page offers flexibility in the application board production line, as it can be used to store unique identification parameters and/or parameters specific to the production line. Figure 1. Logic diagram
The memory array is organized as 65536 x 8 bit. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD).
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M95512-W, M95512-R Table 1. Signal names
Signal name C D Q S W HOLD VCC VSS Function Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply voltage Ground Input Input Output Input Input Input
Description
Direction
Caution:
As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light. Figure 2. SO8, TSSOP8 and UFDFPN8 connections
1. See Section 11: Package mechanical data for package dimensions, not and how to identify pin-1.
Figure 3.
WLCSP connections (top view, marking side, with balls on the underside)
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Signal description
M95512-W, M95512-R
2
Signal description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 13 and Table 15). These signals are described next.
2.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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Doc ID 11124 Rev 13
M95512-W, M95512-R
Signal description
2.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
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Connecting to the SPI bus
M95512-W, M95512-R
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 4. Bus master and memory devices on the SPI bus
VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD SPI Bus Master R CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI Memory Device VCC VSS R SPI Memory Device CQD VCC VSS R SPI Memory Device CQD VCC VSS
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance. The pull-up resistor R (represented in Figure 4) ensures that no device is selected if the Bus Master leaves the S line in the high impedance state. In applications where the Bus Master might enter a state where all inputs/outputs SPI lines are in high impedance at the same time (for example, if the Bus Master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high). This ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 k,.
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M95512-W, M95512-R
Connecting to the SPI bus
3.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
 
CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
 
C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) SPI modes supported
Figure 5.
CPOL CPHA C
0
0
1
1
C
D
MSB
Q
MSB
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Operating features
M95512-W, M95512-R
4
4.1
4.1.1
Operating features
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8 and Table 10.). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
4.1.2
Device reset
In order to prevent inadvertent Write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the POR threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 8 and Table 10). When VCC passes over the POR threshold, the device is reset and in the following state:
 
in the Standby Power mode deselected (note that when the device is deselected it is necessary to apply a falling edge on Chip Select (S) prior to issuing any new instruction, otherwise the instruction is not executed) Status register values: - - - the Write Enable Latch (WEL) bit is reset to 0 the Write In Progress (WIP) bit is reset to 0 the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).

When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode, however, the device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8 and Table 10.
4.1.3
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 4). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 8 and Table 10 and the rise time must not vary faster than 1 V/s.
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Operating features
4.1.4
Power-down
During power-down (continuous decrease in VCC below the minimum VCC operating voltage defined in Table 8 and Table 10), the device must be:
 
deselected (Chip Select (S) should be allowed to follow the voltage applied on VCC) in Standby Power mode (that is there should not be any internal write cycle in progress).
4.2
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The device consumes ICC, as specified in Table 15. When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1.
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as Serial Clock (C) already being low (as shown in Figure 6). The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as Serial Clock (C) already being low. Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. Figure 6. Hold condition activation
C
HOLD
Hold Condition
Hold Condition
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Operating features
M95512-W, M95512-R
4.4
Status register
Figure 7 shows the position of the Status register in the control logic of the device. The Status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a detailed description of the Status register bits
4.5
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms:
 
Write and Write Status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write (WRITE) instruction completion
 
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only. The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:

The `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). The `next rising edge of Serial Clock (C)' might (or might not) be the next bus transaction for some other device on the SPI bus. Write-protected block size
Status register bits Protected block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory Protected array addresses none C000h - FFFFh 8000h - FFFFh 0000h - FFFFh

Table 2.
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Memory organization
5
Memory organization
The memory is organized as shown in Figure 7. Figure 7.
HOLD W S C D Q Control Logic
Block diagram
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register
Size of the Read only EEPROM area
Y Decoder
1 Page
X Decoder
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Instructions
M95512-W, M95512-R
6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3. M95512-W and M95512-R instruction set
Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Instruction WREN WRDI RDSR WRSR READ WRITE
Table 4.
M95512-DR instruction set
Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 1000 0011(1) 1000 0010(1) 1000 0011(2) 1000 0010(2)
Instruction WREN WRDI RDSR WRSR READ WRITE
Read Identification Reads the page dedicated to identification. Page Write Identification Writes the page dedicated to identification. Page Read Lock Status Lock ID Reads the lock status of the Identification Page. Locks the Identification page in read-only mode.
1. Address bit A10 must be 0, all other address bits are Don't Care. 2. Address bit A10 must be 1, all other address bits are Don't Care.
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Instructions
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. Figure 8. Write Enable (WREN) sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
   
Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Write Disable (WRDI) sequence
S 0 C Instruction D High Impedance Q
AI03750D
Figure 9.
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Instructions
M95512-W, M95512-R
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10. The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 5) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5.
b7 SRWD 0 0 0 BP1 BP0 WEL
Status register format
b0 WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit
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S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 Status Register Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instructions
0
7
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Instructions
M95512-W, M95512-R
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before a WRSR instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Write Status Register (WRSR) instruction is issued by driving Chip Select (S) low, sending the instruction code and the data byte on Serial Data input (D) and driving Chip Select (S) high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed. Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write cycle whose duration is tW (specified in Table 16 and Table 18). The instruction sequence is shown in Figure 11. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is also reset when the Write cycle tW is complete. The Write Status Register (WRSR) instruction allows the user to change the values of the BP1, BP0 and SRWD bits:
 
The Block Protect (BP1, BP0) bits define the size of the area to be treated as read-only, as defined in Table 6. The SRWD bit (Status Register Write Disable bit), depending on the signal applied on the Write Protect pin (W), allows the user to set or reset the write protection mode of the Status Register. When the Status Register is in the Write-protected mode, the Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated upon completion of the WRSR instruction (after tW). The Write Status Register (WRSR) instruction has no effect on Status Register bits b6, b5, b4, b1, b0. They are always read as 0. Figure 11. Write Status Register (WRSR) sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
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8
9 10 11 12 13 14 15
D
6
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MSB
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M95512-W, M95512-R Table 6. Protection modes
Mode Write Protection of the Status Register
Instructions
W SRWD Signal Bit 1 0 1 0 0 1
Memory content Protected area(1) Unprotected area(1)
Status Register is Writable Software (if the WREN instruction Protected has set the WEL bit) Write Protected (SPM) The values in the BP1 and BP0 bits can be changed Status Register is Hardware Hardware write protected Protected The values in the BP1 and Write Protected (HPM) BP0 bits cannot be changed
Ready to accept Write instructions
0
1
Ready to accept Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
The protection features of the device are summarized in Table 6. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction), regardless of the logic level applied on the Write Protect (W) input pin. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W) input pin:
 
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction. If Write Protect (W) is driven low, it is not possible to write to the Status Register even if the WEL bit has previously been set by a WREN instruction (attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software-protected (SPM) by the Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered either:
 
by setting the SRWD bit after driving the Write Protect (W) input pin low or by driving the Write Protect (W) input pin low after setting the SRWD bit
Once entered, the Hardware-protected mode (HPM) can only be exited by pulling Write Protect (W) high. If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can never be activated, and only the Software-protected mode (SPM) using the Block Protect (BP1, BP0) bits in the Status Register, can be used.
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Instructions
M95512-W, M95512-R
6.5
Read from Memory Array (READ)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 12. Read from Memory Array (READ) sequence
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
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Instructions
6.6
Write to Memory Array (WRITE)
As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle triggered by the rising edge of Chip Select (S) continues for a period tW (as specified in Table 16 and Table 18), at the end of which the Write in Progress (WIP) bit is reset to 0. In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. If, though, Chip Select (S) continues to be driven low, as shown in Figure 14., the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 128 bytes). The instruction is not accepted, and is not executed, under the following conditions:
   
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a Write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Note:
The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as "0" and a programmed bit is read as "1". Figure 13. Byte Write (WRITE) sequence
S 0 C Instruction 16-Bit Address Data Byte 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13
3
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1
0
7
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Instructions Figure 14. Page Write (WRITE) sequence
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10
M95512-W, M95512-R
20 21 22 23 24 25 26 27 28 29 30 31
Data Byte 1
D
15 14 13
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2
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S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 Data Byte 3 Data Byte N
D
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Instructions
6.7
Read Identification Page (available only in M95512-DR devices)
The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D). Address bit A10 must be 0, address bits [A15:A11] and [A9:A7] are Don't Care, and the data byte pointed to by [A6:A0] is shifted out on Serial Data output (Q). If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the ID page from location 90d, the number of bytes should be less than or equal to 38d, as the ID page boundary is 128 bytes). The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 15. Read Identification Page sequence
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Instructions
M95512-W, M95512-R
6.8
Write Identification Page (available only in M95512-DR devices)
The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Table 4), the Chip Select signal (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in on Serial Data input (D). Address bit A10 must be 0, address bits [A15:A11] and [A9:A7] are Don't Care, the [A6:A0] address bits define the byte address inside the identification page. The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed write cycle triggered by the rising edge of Chip Select (S) continues for a period tW (as specified in Table 17 and Table 18), at the end of which the Write in Progress (WIP) bit is reset to 0. In the case of Figure 16, Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. However, if Chip Select (S) continues to be driven low, as shown in Figure 16, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 128 bytes). The instruction is not accepted, and is not executed, under the following conditions:
    
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction) if Status register bits (BP1, BP0) = (1, 1) if a write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that was latched in) if the Identification page is locked by the Lock Status bit
Figure 16. Write Identification Page sequence
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Instructions
6.9
Read Lock Status (available only in M95512-DR devices)
The Read Lock Status instruction (see Table 4) allows to check if the Identification Page is locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q). It is at `1' when the lock is active and at `0' when the lock is not active. If Chip Select (S) continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is shown in Figure 17.
Figure 17. Read Lock Status sequence
6.10
Lock ID (available only in M95512-DR devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data input (D), and driving Chip Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Lock ID instruction is not executed. Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration is tW (specified in Table 17 and Table 18). The instruction sequence is shown in Figure 18.
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Instructions
M95512-W, M95512-R
The instruction is not accepted, and so not executed, under the following conditions:
    
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction) if Status register bits (BP1,BP0) = (1,1) if a write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that was latched in) if the Identification page is locked by the Lock Status bit
Figure 18. Lock ID sequence
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ECC (error correction code) and write cycling
7
ECC (error correction code) and write cycling
The M95512-W, M95512-R and M95512-DR devices offer an ECC (error correction code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word. It is therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of Write cycles. The M95512-W, M95512-R and M95512-DR devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets.
8
8.1
Power-up and delivery state
Power-up state
After power-up, the device is in the following state:
    
Standby Power mode Deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). Not in the Hold Condition Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits).
8.2
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
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Maximum rating
M95512-W, M95512-R
9
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7.
Symbol
Absolute maximum ratings
Parameter Ambient temperature with power applied -40 -65 see note -0.50 -0.50 -5 -0.50 -3000 Min. 130 150
(1)
Max. C C C V V mA mA V V
Unit
TSTG TLEAD VO VI IOL IOH VCC VESD
Storage temperature Lead temperature during soldering Output voltage Input voltage DC output current (Q = 0) DC output current (Q = 1) Supply voltage Electrostatic discharge voltage (human body model)(2)
VCC+0.6 6.5 5 6.5 +3000
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100pF, R1=1500 , R2=500 )
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DC and AC parameters
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8.
Symbol VCC TA Supply voltage Ambient operating temperature (device grade 6)
Operating conditions (M95512-W device grade 6)
Parameter Min. 2.5 -40 Max. 5.5 85 Unit V C
Table 9.
Symbol VCC TA
Operating conditions (M95512-W device grade 3)
Parameter Supply voltage Ambient operating temperature (device grade 6) Min. 2.5 -40 Max. 5.5 125 Unit V C
Table 10.
Symbol VCC TA
Operating conditions (M95512-R and M95512-DR)
Parameter Supply voltage Ambient operating temperature Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 11.
Symbol CL
AC measurement conditions
Parameter Load capacitance Input Rise and Fall times Input Pulse voltages Input and output timing reference voltages Min. 30 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 19. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
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DC and AC parameters Table 12.
Symbol COUT CIN
M95512-W, M95512-R Capacitance(1)
Parameter Test condition VOUT = 0 V VIN = 0 V VIN = 0 V Min. Max. 8 8 6 Unit pF pF pF
Output capacitance (Q) Input capacitance (D) Input capacitance (other pins)
1. Not 100% tested.
Table 13.
Symbol ILI ILO
DC characteristics (current(1) M95512-W products)
Parameter Test conditions: VCC = 2.5 to 5.5 V at TA = -40 to 85 C (device grade 6) or TA = -40 to 125 C (device grade 3) VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open During tW, S = VCC, 2.5 V < VCC < 5.5 V S = VCC, VIN = VSS or VCC, 2.5 V < VCC < 5.5 V -0.45 0.7 VCC VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA VCC = 2.5 V and IOH = -0.4 mA or VCC = 5 V and IOH = -2 mA 0.8 VCC Min. Max. 2 2 3 5 6 5 0.3 VCC VCC+1 0.4 Unit A A mA mA mA A V V V V
Input leakage current Output leakage current
ICC
Supply current (Read)
ICC0(2) ICC1 VIL VIH VOL VOH
Supply current (Write) Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage
1. Current products are identified by AB process letters AB. 2. Characterized value, not tested in production.
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M95512-W, M95512-R Table 14.
Symbol ILI ILO
DC and AC parameters
DC characteristics (new(1) M95512-W products)
Parameter Input leakage current Output leakage current Test conditions: VCC = 2.5 to 5.5 V, TA = -40 to 85 C VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 10 MHz, VCC = 2.5 V, Q = open C = 0.1VCC/0.9VCC at 20 MHz, VCC = 5 V, Q = open During tW, S = VCC, 2.5 V < VCC < 5.5 V S = VCC, VIN = VSS or VCC, 2.5 V < VCC < 5.5 V -0.45 0.7 VCC VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA VCC = 2.5 V and IOH = -0.4 mA or VCC = 5 V and IOH = -2 mA 0.8 VCC Min. Max. 2 2 4 8 6 5 0.3 VCC VCC+1 0.4 Unit A A mA mA mA A V V V V
ICC
Supply current (Read)
ICC0(2) ICC1 VIL VIH VOL VOH
Supply current (Write) Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage
1. New products are identified by process letter K. 2. Characterized value, not tested in production.
Table 15.
Symbol ILI ILO
DC characteristics (current and new M95512-R and M95512-DR products)
Parameter Input leakage current Output leakage current Test conditions: VCC = 1.8 to 5.5 V, TA = -40 to 85 C VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 2 MHz, VCC = 1.8 V, Q = open(1) C = 0.1VCC/0.9VCC at 5 MHz, VCC = 1.8 V, Q = open(2) During tW, S = VCC, 1.8 V < VCC < 2.5 V S = VCC, VIN = VSS or VCC, 1.8 V < VCC < 2.5 V -0.45 0.7 VCC IOL = 0.15 mA, VCC = 1.8 V IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC Min Max 2 2 1 2.5 3 3 0.3 VCC VCC+1 0.3 Unit A A mA mA mA A V V V V
ICC
Supply current (Read)
ICC0(3) ICC1 VIL VIH VOL VOH
Supply current (Write) Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage
1. Current products are identified by process letters AB. 2. New products are identified by process letter K. 3. Characterized value, not tested in production.
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DC and AC parameters Table 16. AC characteristics (current(1) M95512-W products)
Test conditions:
M95512-W, M95512-R
VCC = 2.5 to 5.5 V at TA = -40 to 85 C (device grade 6) or TA = -40 to 125 C (device grade 3) Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH tCL
(2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency S active setup time
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH (3) tCHCL
(3)
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ (3) tCLQV tCLQX tQLQH
(3)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tQHQL (3) tHHQV tHLQZ tW
(3)
1. Current products are identified by process letters AB. 2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 3. Value guaranteed by characterization, not 100% tested in production.
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M95512-W, M95512-R Table 17. AC characteristics (New(1) M95512-W products)
Test conditions: VCC = 2.5 to 5.5 V, TA = -40 to 85 C Min. Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH tCL
(2) (2) (3)
DC and AC parameters
Max.
Min.
Max. Unit
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency
Parameter 2.5 V to 5.5 V D.C. 30 30 40 30 30 45 45 2 2 10 10 30 30 0 0 40 40 0 40 40 40 40 5 0 20 20 20 20 5 5 10 15 15 0 0 20 20 10 4.5 V to 5.5 V D.C. 15 15 20 15 15 20 20 2 2 20
MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
S active setup time S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH
tCHCL (3) tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(3)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tCLQV tCLQX tQLQH tQHQL
(3) (3)
tHHQV tHLQZ tW
(3)
1. New products are identified by process letter K. 2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 3. Value guaranteed by characterization, not 100% tested in production.
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DC and AC parameters Table 18.
M95512-W, M95512-R
AC characteristics (current and new M95512-R and M95512-DR products)
Test conditions: VCC = 1.8 to 5.5 V, TA = -40 to 85 C Min. Max. Min. Max. Unit MHz ns ns ns ns ns ns ns 2 2 20 20 60 60 0 0 250 150 0 100 100 100 250 5 0 80 80 80 80 5 80 80 s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH tCL
(3) (3) (4)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency
Parameter
Current(1) products New products(2) D.C. 200 200 200 200 200 200 200 1 1 40 50 140 90 0 0 2 D.C. 60 60 90 60 60 80 80 5
S active setup time S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH
tCHCL (4) tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(4)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time
tCLQV tCLQX tQLQH tQHQL
(4) (4)
tHHQV tHLQZ tW
(4)
1. Current products are identified by process letters "AB". 2. New products are identified by process letter K. For these new products, the test flow guarantees the AC parameter values defined in this table (when VCC = 1.8 V) and the AC parameter values defined in Table 17 (when VCC= 2.5 V or VCC= 5.0 V). 3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 4. Value guaranteed by characterization, not 100% tested in production.
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M95512-W, M95512-R Figure 20. Serial input timing
DC and AC parameters
tSHSL S tCHSL C tDVCH tCHCL tCHDX D MSB IN LSB IN tCL tCLCH tSLCH tCH tCHSH tSHCH
Q
High impedance
AI01447d
Figure 21. Hold timing
S tHLCH tCLHL C tCLHH tHLQZ Q tHHQV tHHCH
HOLD
AI01448c
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DC and AC parameters Figure 22. Serial output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D LSB IN
ADDR
M95512-W, M95512-R
tSHSL
tCLCH
tCHCL
tCL
tSHQZ
AI01449f
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Package mechanical data
11
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 23. SO8N - 8 lead plastic small outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 19.
SO8N - 8 lead plastic small outline, 150 mils body width, package mechanical data
millimeters inches(1) Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 5.00 6.20 4.00 - 0.50 8 1.27 0.0409 0.1929 0.2362 0.1535 0.05 0.189 0.2283 0.1496 0.0098 0 0.0157 0.25 0.0039 0.0492 0.011 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 0.0197 8 0.05 Typ Min Max 0.0689 0.0098
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M95512-W, M95512-R
Figure 24. TSSOP8 - 8 lead thin shrink small outline, package outline
D
8
5
c
E1 E
1
4

A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 20.
Symbol
TSSOP8 - 8 lead thin shrink small outline, package mechanical data
millimeters Typ Min Max 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0 8 8 2.900 - 6.200 4.300 0.450 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ inches(1) Min Max 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295
A A1 A2 b c CP D e E E1 L L1  N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
Figure 25. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, package outline
D L3 e b L1
E
E2
L A D2 ddd A1
UFDFPN-01
1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 21.
UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 .mm, package mechanical data
millimeters inches(1) Max 0.60 0.05 0.30 2.10 1.70 0.08 3.00 0.20 0.50 0.45 2.90 0.10 - 0.40 3.10 0.30 - 0.50 0.15 0.30 0.0118 0.1181 0.0079 0.0197 0.0177 0.1142 0.0039 - 0.0157 Typ 0.0217 0.0008 0.0098 0.0787 0.0630 Min 0.0197 0 0.0079 0.0748 0.0591 Max 0.0236 0.0020 0.0118 0.0827 0.0669 0.0031 0.1220 0.0118 - 0.0197 0.0059
Symbol Typ A A1 b D D2 ddd E E2 e L L1 L3 0.55 0.02 0.25 2.00 1.60 Min 0.50 0.00 0.20 1.90 1.50
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M95512-W, M95512-R
Figure 26. WLCSP-R - 8-bump wafer-length chip-scale package outline
e1 D
X Y Orientation reference
e3
Orientation reference
Detail A E
A B C D E 1 2 F Bump side 3
e2 e G
aaa
Wafer back side
A2 A Side view
Bump
eee Z
A1
Detail A rotated by 90 C
Z
b
Seating plane
ME_1Cc
1. Drawing is not to scale.
Table 22.
WLCSP-R - 8-bump wafer-length chip-scale package mechanical data
millimeters inches(1) Max 0.670 Typ 0.0228 0.0091 0.0138 0.0127 1.548 2.016 0.0564 0.0748 0.0394 0.0341 0.0197 0.0170 0.0112 0.0178 8 0.110 0.060 0.0043 0.0024 0.0609 0.0794 Min 0.0193 Max 0.0264
Symbol Typ A A1 A2 b(2) D E e e1 e2 e3 F G N (number of terminals) aaa eee 0.580 0.230 0.350 0.322 1.433 1.901 1.000 0.866 0.500 0.433 0.284 0.453 8 Min 0.490
1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Measured at the maximum bump diameter parallel to primary datum Z.
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Part numbering
12
Part numbering
Table 23.
Example: Device type M95 = SPI serial access EEPROM Device function 512 = 512 Kbit (65536 x 8) 512-D = 512 Kbit (65536 x 8) plus Identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V Package MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MB = UFDFPN8 (MLP8) CS = WLCSP Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Device tested with high reliability certified flow(1). Automotive temperature range (-40 to 125 C)
Ordering information scheme
M95512 - W MN 6 T P /AB
Option blank = Standard packing T = Tape and reel packing Plating technology P or G = ECOPACK(R) (RoHS compliant) Process(2) /AB = F8L /K = F8H
1. ST strongly recommends the use of the automotive grade devices for use in an automotive environment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
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Part numbering
M95512-W, M95512-R
2. The process letters only appear in the product ordering codes of device grade 3 devices. For other devices, it is only given here as an indication of how to differentiate current from new products. To identify current from new devices, please contact your nearest ST sales office.
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 24. Available M95512 products (package, voltage range, temperature grade)
Package SO8 (MN) TSSOP (DW) UFDFPN8 (MB) WLCSP (CS) M95512-W 2.5 V to 5.5 V Range 6, range 3 Range 6 M95512-R 1.8 V to 5.5 V Range 6 Range 6 Range 6 Range 6
Table 25.
Available M95512-DR products (package, voltage range, temperature grade)
Package M95512-DR 1.8 V to 5.5 V Range 6 Range 6
SO8 (MN) TSSOP (DW)
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Revision history
13
Revision history
Table 26.
Date Jan-1999
Document revision history
Revision 1.0 Document written Document reformatted using the new template Voltage range -S added, and -R removed Instruction Sequence illustrations updated Announcement made of planned upgrade to 10 MHz clock for the 5V, -40 to 85C, range Table of contents, and Pb-free options added. VIL(min) improved to 0.45V. Voltage range -R added, and -S removed Old versions of document completely replaced by one rewritten from M95256 AC and DC characteristics tables updated with the performance data of the new device identified with the process letter "A". Table 1., Product List added. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX, tCHHL and tCHHH corrected to tHHQV, tCLHL and tCLHH, respectively. M95512 part number with 4.5V to 5.5V operating voltage range removed (related tables removed). Document status changed to Preliminary Data. Updated Figure 4: Bus master and memory devices on the SPI bus and Figure 21: Hold timing. Power On Reset information clarified. Protected Array Addresses modified in Table 2: Write-protected block size. Ambient Operating Temperature value added in Table 7: Absolute maximum ratings. Supply Current (ICC) value modified for 10 MHz in Table 13: DC characteristics (current M95512-W products). All values modified in Table 18: AC characteristics (current and new M95512-R and M95512-DR products). Document status changed to Datasheet. Changes
13-Feb-2002
2.0
05-Dec-2003 02-Apr-2004
3.0 4.0
03-Jan-2005
5.0
30-Jun-2005
6.0
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Revision history Table 26.
Date
M95512-W, M95512-R Document revision history (continued)
Revision Changes Document reformatted. Packages are ECOPACK(R) compliant. 10 MHz frequency removed. VCC supply voltage and VSS ground descriptions added. Figure 4: Bus master and memory devices on the SPI bus modified and explanatory paragraph added. Power-up and Power On Reset paragraphs replaced by Section 4.1: Supply voltage (VCC). Section 7: ECC (error correction code) and write cycling added. TA max modified in Table 8: Operating conditions (M95512-W device grade 6). Note modified below Table 12: Capacitance. CL modified in and Table 11: AC measurement conditions. VIL max and ICC0 test conditions modified in Table 15: DC characteristics (current and new M95512-R and M95512-DR products). ICC modified in Table 13: DC characteristics (current M95512-W products), ICC0 added to Table 13 and Table 15: DC characteristics (current and new M95512-R and M95512-DR products) modified. Table 18: AC characteristics (current and new M95512-R and M95512-DR products) modified. tSHQZ end timing line moved back in Figure 22: Serial output timing. SO8N package specifications updated (see Figure 23 and Table 19). Blank removed below Plating technology in Table 23: Ordering information scheme. The device endurance is specified at more than 1 000 000 (1 million) cycles (corrected on cover page). M95512-W is now available in the device grade 3 (automotive temperature range), see Table 8 on page 31). Section 4.1: Supply voltage (VCC) on page 12 updated. Section 6.4: Write Status Register (WRSR) on page 20 and Section 6.6: Write to Memory Array (WRITE) on page 23 clarified. ICC0 modified in Table 13: DC characteristics (current M95512-W products). Figure 20: Serial input timing, Figure 21: Hold timing and Figure 22: Serial output timing updated. Package mechanical data values in inches are calculated from the millimeter values and rounded to four decimal digits (see Section 11: Package mechanical data). Table 24: Available M95512 products (package, voltage range, temperature grade) added. Small text changes. M95512-DR part number added (see Table 25: Available M95512-DR products (package, voltage range, temperature grade)). New M95512-W, M95512-R and M95512-DR products operating at up to 20 MHz added (preliminary data). UFDFPN8 package added (see Section 11: Package mechanical data).
06-Feb-2007
7
05-Jun-2007
8
03-Jul-2008
9
14-Apr-2009
10
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M95512-W, M95512-R Table 26.
Date
Revision history Document revision history (continued)
Revision Changes VESD modified in Table 7: Absolute maximum ratings. Updated: - Section 6.7: Read Identification Page (available only in M95512-DR devices) - Section 6.8: Write Identification Page (available only in M95512-DR devices) - Section 6.9: Read Lock Status (available only in M95512-DR devices) - Section 6.10: Lock ID (available only in M95512-DR devices) Data related to new products are no longer preliminary. Note 2 updated in Table 18: AC characteristics (current and new M95512R and M95512-DR products). WLCSP package added. M95512-DR added. Updated: - Section 1: Description - Section 6.7: Read Identification Page (available only in M95512-DR devices) - Section 6.8: Write Identification Page (available only in M95512-DR devices) - Section 6.9: Read Lock Status (available only in M95512-DR devices), Table 7: Absolute maximum ratings Inserted Caution under Table 1: Signal names Added Note under Figure 24: TSSOP8 - 8 lead thin shrink small outline, package outline
11-May-2009
11
28-Aug-2009
12
14-Sep-2010
13
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M95512-W, M95512-R
Please Read Carefully:
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