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Samsung Electronic
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| Part No. |
M381L3223CTL
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| OCR Text |
...e(tis/tih) at slow slew rate in ddr200/266 ac specification - deleted exit self refresh to write command(txsw) in ddr200/266 ac specification - rename txsa(exit self refresh to bank active command) to txsnr(exit self refresh to non read c... |
| Description |
32Mx72 DDR SDRAM 184pin DIMM based on 32Mx8 Data Sheet
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| File Size |
174.62K /
16 Page |
 View
it Online |
Download Datasheet
|
| |
|
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Samsung Electronic
|
| Part No. |
M368L3223CTL
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| OCR Text |
...e(tis/tih) at slow slew rate in ddr200/266 ac specification 5. deleted exit self refresh to write command(txsw) in ddr200/266 ac specification 6. changed unit of tmrd from tck to ns at ddr333 7. rename txsa(exit self refresh to bank active ... |
| Description |
32Mx64 DDR SDRAM 184pin DIMM based on 32Mx8 Data Sheet
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| File Size |
94.43K /
16 Page |
View
it Online |
Download Datasheet |
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Samsung Electronic
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| Part No. |
M368L0914DT2
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| OCR Text |
...arge; trc=trcmin;tck=100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle idd0 - - operating current - one bank operation ; one bank ... |
| Description |
8Mx64 DDR SDRAM 184pin DIMM based on 8Mx16 Data Sheet
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| File Size |
93.17K /
16 Page |
View
it Online |
Download Datasheet |
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Samsung Electronic
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| Part No. |
M381L6523MT1
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| OCR Text |
...arge; trc=trcmin;tck=100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle idd0 - - operating current - one bank operation ; one bank ... |
| Description |
64Mx72 DDR SDRAM 184pin DIMM based on 64Mx8 Data Sheet
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| File Size |
90.59K /
14 Page |
View
it Online |
Download Datasheet |
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SAMSUNG[Samsung semiconductor]
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| Part No. |
M470L6423CK0
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| OCR Text |
...arge; tRC=tRCmin;tCK=100Mhz for ddr200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating current - One bank operation ; One bank open, BL=4... |
| Description |
512MB DDR SDRAM MODULE (64Mx64 based on DDP 64Mx 8 DDR SDRAM) 200pin SODIMM 64bit Non-ECC/Parity
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| File Size |
107.08K /
14 Page |
View
it Online |
Download Datasheet |
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Samsung Electronic
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| Part No. |
M368L1713CT1
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| OCR Text |
...arge; trc=trcmin;tck=100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle idd0 - - operating current - one bank operation ; one bank ... |
| Description |
16Mx64 DDR SDRAM 184pin DIMM based on 16Mx8 Data Sheet
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| File Size |
128.41K /
14 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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