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25V10 56321 KLPC1900 200BG 13002 AD7575TQ LBN70 DTA143E
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  ecl pecl Datasheet PDF File

For ecl pecl Found Datasheets File :: 2878    Search Time::2.062ms    
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    ADCMP580-16

Analog Devices
Part No. ADCMP580-16
OCR Text ...dcmp580/ adcmp581/ adcmp582 cml/ecl/ pecl 04672-001 figure 1. general description the adcmp580 / adcmp581 / adcmp582 are ultrafast voltage comparators fabricated on the analog devices, inc. proprietary xfcb3 silicon germanium (sige)...
Description Ultrafast SiGe Voltage Comparators

File Size 410.65K  /  16 Page

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    Microchip
Part No. SY10ELT23LZG SY10ELT23LZG-TR
OCR Text ...slators. because pecl (positive ecl) levels areused, only +5v and ground are required. the small outline 8-lead soic package and the low skew dual gate design of the elt23 makes it ideal for applications which require the translation of a c...
Description Clock and Timing - Clock and Data Distribution

File Size 54.54K  /  5 Page

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    Microchip
Part No. SY100S834LZG-TR
OCR Text ... a differential or single-ended ecl or, if positive power supplies are used, pecl input signal. in addition, by using the vbb output, a sinu soidal source can be ac- coupled into the device. if a single-ended input is to be used, the vbb...
Description Clock and Timing - Clock and Data Distribution

File Size 180.55K  /  8 Page

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    MC100LVEP210 MC100LVEP210FA MC100LVEP210FAR2 ON0546

ONSEMI[ON Semiconductor]
Part No. MC100LVEP210 MC100LVEP210FA MC100LVEP210FAR2 ON0546
OCR Text ... in Pecl mode, or VEE -3.0V in ecl mode. Designers can take advantage of the LVEP210's performance to distribute low skew clocks across the backplane or the board. In a LVPecl environment, series or Thevenin line terminations are typically...
Description Low-Voltage 1:5 Dual Diff.LVecl/LVPecl/LVEPecl/HSTL Clock Driver 100LVE SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
From old datasheet system

File Size 135.25K  /  8 Page

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    Microchip
Part No. SY100EL91LZG-TR
OCR Text ...y100el91l is a triple lvpecl-to-ecl or lvpecl-to-lvecl translator. a v bb output is provided for interfacing with single ended pecl signals at the input. if a single ended inputis to be used, the v bb output should be connected to the d i...
Description Clock and Timing - Clock and Data Distribution

File Size 81.48K  /  6 Page

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    MC10EP016 MC10EP016FA MC10EP016FAR2 MC100EP016FAR2 MC100EP016 MC100EP016FA

ONSEMI[ON Semiconductor]
Part No. MC10EP016 MC10EP016FA MC10EP016FAR2 MC100EP016FAR2 MC100EP016 MC100EP016FA
OCR Text ecl 8-Bit Synchronous Binary Up Counter The MC10/100EP016 is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Archi...Pecl Mode Operating Range: VCC = 3.0 V to 5.5 V * * * * * * * * * * with VEE = 0 V Necl Mode Operat...
Description GT 7C 7#12 PIN RECP LINE 100EP SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQFP32
3.3V / 5Vecl 8-Bit Synchronous Binary Up Counter 3.3 / 5V的ecl 8位二进制计数器同步最
3.3V / 5Vecl 8-Bit Synchronous Binary Up Counter 10E SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQFP32
3.3V / 5Vecl 8-Bit Synchronous Binary Up Counter 100EP SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQFP32

File Size 110.67K  /  12 Page

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    AN1406D

ON Semiconductor
Part No. AN1406D
OCR Text ...red by cleon petty todd pearson ecl applications engineering this application note provides detailed information on designing with positive emitter coupled logic (pecl) devices. introduction pecl, or positive emitter coupled logic, is nothi...
Description DESIGNING

File Size 92.34K  /  8 Page

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