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Integrated Device Technology, Inc.
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Part No. |
IDT82V3012PV
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OCR Text |
... f0_sel0 f0_sel1 freerun normal holdover tdo tdi mon_out0 fref1 fref0 in_sel virtual reference flock invalid input signal detection f19o c6o jtag lock mode_sel0 mode_sel1 tie_en tms trst tck v dd v ss v dd v dd v ss rst f32o feedback signal... |
Description |
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS SPECIALTY TELECOM CIRCUIT, PDSO56
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File Size |
370.84K /
30 Page |
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it Online |
Download Datasheet |
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Maxim Integrated Products, Inc.
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Part No. |
MAX3953UGK-D
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OCR Text |
...g data becomes invalid, a clock holdover function is provided to maintain a valid reference clock to the upstream device. for proper operation, a reference clock of baud rate/64 or baud rate/16 is required. the max3953 operates from a singl... |
Description |
10Gbps 1:16 Deserializer with Clock Recovery SPECIALTY TELECOM CIRCUIT, QCC68
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File Size |
242.57K /
11 Page |
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it Online |
Download Datasheet |
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Integrated Device Technology, Inc.
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Part No. |
IDT82V3010PVG
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OCR Text |
...e of 1 s ? jtag boundary scan ? holdover status indication ? freerun status indication ? normal status indication ? lock status indication ? input reference quality indication ? 3.3 v operation with 5 v tolerant i/o ? package: 56-pin ssop (... |
Description |
T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS SPECIALTY TELECOM CIRCUIT, PDSO56
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File Size |
350.36K /
31 Page |
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it Online |
Download Datasheet |
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Analog Devices, Inc.
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Part No. |
AD9547BCPZ-REEL7
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OCR Text |
...supports stratum 2 stability in holdover mode supports reference switchover with phase build-out supports hitless reference switchover automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair c... |
Description |
Dual/Quad Input Network Clock Generator/Synchronizer; Package: 64-LFCSP (Leadform Chip Scale); Temperature Range: -40°C to 125°C 450 MHz, OTHER CLOCK GENERATOR, QCC64
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File Size |
966.79K /
104 Page |
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it Online |
Download Datasheet |
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Price and Availability
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