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  idle a Datasheet PDF File

For idle a Found Datasheets File :: 12612    Search Time::1.14ms    
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    DATA DEVICE CORP
Part No. BUS-65142-850L DaTaDEVICECORP-BUS-65142-370S
OCR Text ... (bu-65142x3) current drain  idle  25% transmitter duty cycle  50% transmitter duty cycle  100% transmitter duty cycle -15v (bu-65...a ma ma a v v v 0.7 0.2 0.2 20 0.4 0.4 20 2.4 0.04 0.04 2.4 2.4 2.4 logic v ih v il i ih (v ih =2.7v...
Description 2 CHaNNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, QIP78

File Size 249.79K  /  26 Page

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    Vishay Semiconductors
Part No. TFBS4652-TR3
OCR Text ... ? low current consumption 75 a idle at 3.6 v ? operates from 2.4 v to 3.6 v within specification over full temperature range from - 25 c to + 85 c ? split power supply, emitter can be driven by a separate power supply not loading the regul...
Description IC SPECIaLTY INTERFaCE CIRCUIT, SMa7, 6.80 X 2.80 MM, 1.60 MM HEIGHT, ROHS COMPLIaNT, SMT-7, Interface IC:Other

File Size 225.48K  /  11 Page

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    INTEL CORP
Part No. LD80C51BH-24
OCR Text ... testing power control modes ? idle ? power down memor y organization progra m memory : u p t o 4 kbyte s o f th e progra m memor y ca n re...a memory : thi s microcontrolle r ha s a 12 8 x 8 on-chi p ram . i n additio n i t ca n addres s u p...
Description 8-BIT, MROM, 24 MHz, MICROCONTROLLER, CDIP40
8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40

File Size 1,554.69K  /  20 Page

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    ATTINY1634-MUR ATTINY1634R-SUR ATTINY1634-SUR ATTINY1634R-MU ATTINY1634R-MUR ATTINY1634-UUR

ATMEL Corporation
Part No. aTTINY1634-MUR aTTINY1634R-SUR aTTINY1634-SUR aTTINY1634R-MU aTTINY1634R-MUR aTTINY1634-UUR
OCR Text ...nterrupt on 18 pins ? low power idle, adc noise reduction, standby and power-down modes ? enhanced power-on reset circuit ? programmable br...a low le vel on this pin for longer than the minimum pulse le ngth will generate a reset, even if ...
Description 8-bit atmel tinyaVR Microcontroller with 16K Byres In-System Programmable Flash

File Size 493.69K  /  18 Page

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    XPC8260ZUIFBC

Freescale Semiconductor, Inc
Part No. XPC8260ZUIFBC
OCR Text ... user) - cell rate by inserting idle/unassigned cells ? receive (rx) updates - cell delineation using bit by bit hec checking and programmab...a counter expires ? overrun (rx cell fifo) and underrun (tx cell fifo) condition produces maskable ...
Description PowerQUICC II Integrated Communications Processor Hardware Specifications

File Size 793.34K  /  50 Page

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    EM658160 EM658160TS-33 EM658160TS-35 EM658160TS-4 EM658160TS-5 EM658160TS-6 EM658160TS-7 EM658160TS-8

ETRON[Etron Technology, Inc.]
ETRON[Etron Technology Inc.]
Part No. EM658160 EM658160TS-33 EM658160TS-35 EM658160TS-4 EM658160TS-5 EM658160TS-6 EM658160TS-7 EM658160TS-8
OCR Text ... low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. Bank Select:...a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. Data Input Mask: Inpu...
Description 4M x 16 DDR Synchronous DRaM (SDRaM)

File Size 154.94K  /  26 Page

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    TS80C31X2-LIA

TEMIC SEMICONDUCTORS
Part No. TS80C31X2-LIa
OCR Text ...on in power consumption. in the idle mode the cpu is frozen while the timers, the serial port and the interrupt system are still operating. ...a 3/b 4/c 5/d 6/e 7/f f8h ffh f0h b 0000 0000 f7h e8h efh e0h acc 0000 0000 e7h d8h dfh d0h psw 00...
Description 8-BIT, 30 MHz, MICROCONTROLLER, PDIP40

File Size 161.48K  /  42 Page

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    ZR36015 ZR36015PQC-30

ETC
Part No. ZR36015 ZR36015PQC-30
OCR Text ... High impedance during RESET or idle modes. When SPH is active (High), PXDaTa(7:0) is controlled by the Host Interface. It will be high impedance except during a Host read access, in which case it will be driven. The state of PXDaTa(15:8) f...
Description RaSTER TO BLOCK CONVERTER

File Size 164.91K  /  27 Page

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    ZR36050 ZR36050PQC-21 ZR36050PQC-27

ETC
Part No. ZR36050 ZR36050PQC-21 ZR36050PQC-27
OCR Text ...s and places the ZR36050 in the idle state. RESET can be activated only when CLKEN is asserted and must remain active for a minimum of four CLK_IN cycles. The STaTUS_0, INT_REQ_0, and INT_REQ_1 register bits are reset by this signal. The ST...
Description JPEG IMaGE COMPRESSION PROCESSOR

File Size 262.97K  /  52 Page

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