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Atmel, Corp.
ATMEL CORP
TEMIC SEMICONDUCTORS
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| Part No. |
TSC80C51CXXX-12MYR/883 TSC80C51CXXX-16MYR TSC80C51CXXX-12AYR TSC80C51CXXX-16AYR TSC80C51-16MXB TSC80C31-16ABD TSC80C51-16ABD TSC80C31-20MXB
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| OCR Text |
mhs description the tsc80c31/80c51 is high performance scmos versions of the 8051 nmos single chip 8 bit m c. the fully static design of the tsc80c31/80c51 allows to reduce system power consumption by bringing the clock frequency down to a... |
| Description |
8-BIT, MROM, 12 MHz, MICROCONTROLLER, UUC40 WAFER
8-BIT, MROM, 16 MHz, MICROCONTROLLER, UUC40 WAFER
8-BIT, 16 MHz, MICROCONTROLLER, PQCC44
8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
8-BIT, 20 MHz, MICROCONTROLLER, UUC40
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| File Size |
213.46K /
19 Page |
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Download Datasheet
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Atmel, Corp.
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| Part No. |
SMC9-65608EV-30SB SMDJ-65608EV-30SB TEMICSEMICONDUCTORS-MMC9-65608EV-30/883
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| OCR Text |
...1b figure 2 data retention mode mhs cmos ram ? s are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules insure data retention : 1. during data retention chip ... |
| Description |
128K X 8 STANDARD SRAM, 30 ns, DIP32 0.400 INCH, SIDE BRAZED, DIP-32
128K X 8 STANDARD SRAM, 30 ns, DFP32 0.400 INCH, FP-32
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| File Size |
160.40K /
10 Page |
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it Online |
Download Datasheet |
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Atmel, Corp.
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| Part No. |
SMK2-67025EV-45SB SMK2-67025EV-30SB
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| OCR Text |
...is ? busy lock-out ? problem, mhs has developped a master/slave system which uses a single hardware arbitrator located on the master. the slave has busy inputs which allow direct interface to the master with no external components, givin... |
| Description |
8K X 16 DUAL-PORT SRAM, 45 ns, QFP84 MQFP-84
8K X 16 DUAL-PORT SRAM, 30 ns, QFP84 MQFP-84
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| File Size |
358.32K /
23 Page |
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it Online |
Download Datasheet |
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Atmel, Corp.
ATMEL WIRELESS & MICROCONTROLLERS
TEMIC SEMICONDUCTORS
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| Part No. |
A1P-L67201L-60 A1P-L67201V-60 A1P-L67202L-60 A1P-L67202V-60 A3P-L67201L-60 A3P-L67202L-60 A3P-L67202V-60 A3P-L67201V-60 A1P-L67202L-65 A1P-L67202V-55 ASI-L67201L-60 IUI-L67201L-55
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| OCR Text |
mhs rev. c (10/11/95) 1 introduction the l67201/202 implement a first-in first-out algorithm, featuring asynchronous read/write operations. the full and empty flags prevent data overflow and underflow. the expansion logic allows unlimited ... |
| Description |
512 X 9 OTHER FIFO, 60 ns, CDIP28 0.300 INCH, CERAMIC, DIP-28
1K X 9 OTHER FIFO, 60 ns, CDIP28 0.300 INCH, CERAMIC, DIP-28
512 X 9 OTHER FIFO, 60 ns, PDIP28 0.300 INCH, PLASTIC, DIP-28
1K X 9 OTHER FIFO, 60 ns, PDIP28 0.300 INCH, PLASTIC, DIP-28
1K X 9 OTHER FIFO, 65 ns, CDIP28
1K X 9 OTHER FIFO, 55 ns, CDIP28
512 X 9 OTHER FIFO, 60 ns, PQCC32
512 X 9 OTHER FIFO, 55 ns, PDSO28
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| File Size |
146.80K /
16 Page |
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it Online |
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