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  pll-ii Datasheet PDF File

For pll-ii Found Datasheets File :: 2951    Search Time::0.828ms    
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    CD4046BMS FN3312

INTERSIL[Intersil Corporation]
Part No. CD4046BMS FN3312
OCR Text PLL) consists of a low power linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signalinput ampl...II) * High VCO Linearity: <1% (typ.) at VDD = 10V * VCO Inhibit Control for ON-OFF Keying and Ultra-...
Description From old datasheet system
CMOS Micropower Phase Locked Loop

File Size 108.43K  /  11 Page

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    CYPRESS SEMICONDUCTOR CORP
Part No. CYW15G0101DXB-BBXI
OCR Text ...d loops (plls) with no external pll components dual differential pecl-compatible serial inputs ? internal dc-restoration dual differentia...ii? transceiver is a point-to-point communications building block allowing the transfer of data over...
Description SPECIALTY TELECOM CIRCUIT, PBGA100

File Size 677.58K  /  44 Page

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    CY7C1648KV18-400BZXC CY7C1648KV1812

Cypress Semiconductor
Part No. CY7C1648KV18-400BZXC CY7C1648KV1812
OCR Text ...access port phase locked loop (pll) for accurate data placement configurations with read cycle latency of 2.0 cycles: cy7c1648kv18 ? 8 m 1...ii+ archi- tecture. the ddr ii+ consists of an sram core with advanced synchronous peripheral circu...
Description 144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

File Size 619.29K  /  30 Page

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    CY7C2168KV18 CY7C2170KV18

Cypress Semiconductor
Part No. CY7C2168KV18 CY7C2170KV18
OCR Text ...access port phase locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles: cy7c2168kv18 ? 1 m 1...ii+ architecture. the ddr ii+ consists of an sram core with advanced synchronous peripheral circuitr...
Description 18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

File Size 634.31K  /  29 Page

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    CY7C2163KV18 CY7C2165KV18

Cypress Semiconductor
Part No. CY7C2163KV18 CY7C2165KV18
OCR Text ...access port phase-locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles: cy7c2163kv18 ? 1 m 1...ii+ architecture. similar to qdr ii architecture, qdr ii+ architecture consists of two separate port...
Description 18-Mbit QDR? II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

File Size 630.87K  /  30 Page

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    CY7C1613KV18 CY7C1615KV18

Cypress Semiconductor
Part No. CY7C1613KV18 CY7C1615KV18
OCR Text ... port (tap) phase locked loop (pll) for accurate data placement configuration cy7c1613kv18 ? 8 m 18 cy7c1615kv18 ? 4 m 36 functional desc...ii architecture. qdr ii architecture consists of two separate ports: the read port and the write po...
Description 144-Mbit QDR? II SRAM Four-Word Burst Architecture

File Size 613.95K  /  32 Page

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    INTEGRATED DEVICE TECHNOLOGY INC
Part No. 307G-03LFT
OCR Text ... a 3-wire spi port. an advanced pll coupled to an array of configurable output dividers and three outputs allows low-jitter generation of ...ii software ? directly programmable via versaclock ii software and a windows pc parallel port ? ind...
Description 270 MHz, OTHER CLOCK GENERATOR, PDSO16

File Size 121.29K  /  14 Page

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    Cypress
Part No. CYP15G0201DXB-BBXC CYP15G0201DXB-BBXI
OCR Text ...d loops (plls) with no external pll components optional phase-align buffer in transmit path optional elasticity buffer in receive path d...ii? transceiver is a point- to-point or point-to-multipoint communications building block allowing...
Description Dual-channel HOTLink IITransceiver

File Size 561.69K  /  51 Page

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    INTEGRATED DEVICE TECHNOLOGY INC
Part No. 307G-03
OCR Text ... a 3-wire spi port. an advanced pll coupled to an array of configurable output dividers and three outputs allows low-jitter generation of ...ii software ? directly programmable via versaclock ii software and a windows pc parallel port ? ava...
Description 270 MHz, OTHER CLOCK GENERATOR, PDSO16

File Size 201.66K  /  13 Page

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