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Integrated Device Technology, Inc.
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Part No. |
ICSSSTUAF32866B ICSSSTUAF32866BHLFT
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OCR Text |
...he second register produces to ppo and qerr signals. the qerr of the first register is left floating. the valid error information is latched on the qerr output of the second register. if an error occurs qerr is latched low for two ... |
Description |
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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File Size |
556.95K /
31 Page |
View
it Online |
Download Datasheet
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Integrated Device Technology, Inc.
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Part No. |
ICSSSTUAF32866CHLFT
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OCR Text |
...he second register produces to ppo and qerr signals. the qerr of the first register is left floating. the valid error information is latched on the qerr output of the second register. if an error occurs qerr is latched low for two ... |
Description |
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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File Size |
556.17K /
31 Page |
View
it Online |
Download Datasheet
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Integrated Device Technology, Inc.
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Part No. |
ICSSSTUAF32869AHLF
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OCR Text |
... inputs and will gate the qn, ppo (paritial-parity-out) and ptyerr (parity error) parity outputs from changing states when both dcs and csr are high. if either dcs and csr input is low, the qn, ppo and ptyerr outputs will functio... |
Description |
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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File Size |
418.30K /
21 Page |
View
it Online |
Download Datasheet
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Price and Availability
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