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AMICC[AMIC Technology]
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Part No. |
A48P4616
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OCR Text |
...uency (MHz) DDR400 (5T) 166 200 ddr333 (6K) 133 166 DQS is edge-aligned with data for reads and is centeraligned with data for writes. Differential clock inputs (CK and CK) Four internal banks for concurrent operation. Data mask (DM) for wr... |
Description |
16M X 16 Bit DDR DRAM
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File Size |
2,066.77K /
71 Page |
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it Online |
Download Datasheet
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http://
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Part No. |
W3EG6467S403D4
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OCR Text |
...d* features ddr200, ddr266, ddr333 and ddr400 ? jedec design speci? cations double-data-rate architecture bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2.5 (clock) ... |
Description |
512MB - 2x32Mx64 DDR SDRAM UNBUFFERED
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File Size |
194.16K /
12 Page |
View
it Online |
Download Datasheet
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Price and Availability
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