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LINEAR TECHNOLOGY CORP Linear Technology, Corp.
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Part No. |
LT1719IS6TR LT1719CS6TR LT1719CS6TRMPBF LT1719IS8PBF
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OCR Text |
... v cm = C5.1v to v cm = 3.8v, divided by 8.9v. note 5: the lt1719s6 common mode rejection ratio is measured with v + = 5v and is de? ned as the change in offset voltage measured from v cm = C0.1v to v cm = 3.8v, divided by 3.9v. no... |
Description |
4.5ns Single/Dual Supply 3V/5V Comparator with Rail-to-Rail Output; Package: SO; No of Pins: 8; Temperature Range: -40°C to 85°C COMPARATOR, 3500 uV OFFSET-MAX, 7 ns RESPONSE TIME, PDSO8 4.5ns Single/Dual Supply 3V/5V Comparator with Rail-to-Rail Output; Package: SOT; No of Pins: 6; Temperature Range: 0°C to 70°C COMPARATOR, 3500 uV OFFSET-MAX, 7 ns RESPONSE TIME, PDSO6 4.5ns Single/Dual Supply 3V/5V Comparator with Rail-to-Rail Output; Package: SOT; No of Pins: 6; Temperature Range: -40°C to 85°C COMPARATOR, 3500 uV OFFSET-MAX, 7 ns RESPONSE TIME, PDSO6
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File Size |
210.97K /
22 Page |
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Intersil, Corp.
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Part No. |
ISL5416KIZ
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OCR Text |
...an be ones complemented. can be divided into two 8-bit busses. see data output formatter section and microprocessor interface section. see table 24. bout(15:0) o parallel data output bus b. a 16-bit paralle l data output which can be progr... |
Description |
Four-Channel Wideband Programmable DownConverter TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA256
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File Size |
1,132.33K /
71 Page |
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Electronic Theatre Controls, Inc.
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Part No. |
FS6370-01
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OCR Text |
...or the refer- ence divider. the divided reference is fed into the pfd. the pfd controls the frequency of the vco (f vco ) through the charge pump and loop filter. the vco pro- vides a high-speed, low noise, continuously variable fre- quency... |
Description |
EEPROM Programmable 3-PLL Clock Generator IC EEPROM的可编程3 - PLL时钟发生器芯
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File Size |
1,408.71K /
25 Page |
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Zarlink Semiconductor, Inc.
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Part No. |
ZL38010DCF ZL38010DCE1 ZL38010DCF1
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OCR Text |
...output is the mclk (c4 ) input divided by two, inverted, and synchronized to f0i . this output is high-impedance during ssi operation. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 ms1 vdd ms3 ic ms4 format m... |
Description |
Low Power Quad ADPCM Transcoder A/MU-LAW, ADPCM CODEC, PDSO28
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File Size |
480.87K /
27 Page |
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Cypress Semiconductor, Corp.
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Part No. |
CY22392ZI-XXXT CY22392ZC-XXX CY22392ZC-XXXT
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OCR Text |
...that is equal to the reference divided by an 8-bit divider (q) and multiplied by an 11-bit divider in the pll feedback loop (p). the output of pll1 is sent to the crosspoint switch. the output of pll1 is also sent to a /2, /3, or /4 sync... |
Description |
166 MHz, OTHER CLOCK GENERATOR, PDSO16 4.40 MM, MO-153, TSSOP-16 200 MHz, OTHER CLOCK GENERATOR, PDSO16 4.40 MM, MO-153, TSSOP-16
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File Size |
298.65K /
9 Page |
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Maxim Integrated Products, Inc.
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Part No. |
DS1075Z-60
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OCR Text |
... purposes the register bits are divided into two 9-bit words, the ?mux? word determines mode of operation and prescaler values. the ?div? word sets the value of the programmable divider. mux word figure 2 (msb) (lsb) 0* 0* 0* en0 pdn m m... |
Description |
60 MHz, OTHER CLOCK GENERATOR, PDSO8 0.150 INCH, SO-8
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File Size |
259.33K /
18 Page |
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Fujitsu Microelectronics
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Part No. |
MB86941 MB86941PFV MB86942 MB86942PFV MB86941PVF MB86942PVF
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OCR Text |
...rnal clock, the clock frequency-divided by the prescaler, and the external clock. prescalers 0 and 1 are linked with timer channels 0 and 1, respectively. each of the prescalers is initialized upon loading (or reloading) of the timer init... |
Description |
Microprocessor SPARClite - Peripheral LSI for SPARClite Microprocessor SPARlite Peripheral LSI for SPARClite
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File Size |
247.48K /
49 Page |
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Atmel
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Part No. |
U4256BM
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OCR Text |
...g voltage output. this range is divided into 256 steps. so one step is approximately (2.16 - 0.46) v (pdo) / 255 = 0.005764 v (pdo) . the gain of dac1 can be controlled by the bits 36 to 43 (g-2 0 to g-2 7 ) and the gain of dac2 b... |
Description |
Frequency synthesizer for radio tuning
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File Size |
220.14K /
19 Page |
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