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SIEMENS AG
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| Part No. |
SDA5642-6X Q67100-H5182
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| OCR Text |
...ing those signals to internally generated slicing levels. the output of the sync separator is forwarded, on one hand, to the output pin vcs, and on the other hand, to the clock generator and the timing block. the vcs signal represents a key... |
| Description |
VPS-Decoder(VPS解码
VPS-Decoder TELETEXT AND VPS/PDC DECODER, PDSO20
VPS-Decoder 车辆定位系统解码
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| File Size |
690.23K /
27 Page |
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Zarlink Semiconductor
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| Part No. |
ZL30462
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| OCR Text |
...een the input reference and the generated output clocks. this pin is internally pulled to gnd. 29 reset reset (input). logic 0 will forces the module into a reset state. this pin must be held to logic 0 for a minimum of 1s to reset the m... |
| Description |
Compact Timing Module with 155.52 & 19.44 MHz Outputs
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| File Size |
216.87K /
22 Page |
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it Online |
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Cirrus Logic, Inc.
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| Part No. |
DS1992L-E00
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| OCR Text |
...ee figure 2.) the 1-wire crc is generated using a polynomial gener- ator consisting of a shift register and xor gates as shown in figure 3. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire cyclic re... |
| Description |
(135.97 k) 35.97十一
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| File Size |
137.94K /
20 Page |
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it Online |
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Atmel
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| Part No. |
U211B
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| OCR Text |
...at pin 12, a trig- ger pulse is generated whose width t p is determined by the value of c 2 (the value of c 2 and hence the pulse width can be evaluated by assuming 8 s/nf). at the same time, a latch is set, so that as long as the autom a... |
| Description |
As U209B foldback
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| File Size |
471.92K /
28 Page |
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it Online |
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OKI SEMICONDUCTOR CO., LTD.
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| Part No. |
ML50000
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| OCR Text |
...o (in acoustic or line systems) generated in the communication path. using digital signal processing, the echo path is estimated and a pseudo-echo signal is generated to cancel the echo. when used as an acoustic echo canceler, the device ca... |
| Description |
Echo Canceler(回声消除
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| File Size |
289.04K /
26 Page |
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it Online |
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Zarlink Semiconductor, Inc.
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| Part No. |
MT9125 MT9125APR
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| OCR Text |
... the bit rate, at 2.048 mhz, is generated internally from the master clock input at the mclk pin. the bclk and ena inputs are ignored. data is latched into the adpcmi pin at the three-quarter bit position which occurs at the second rising e... |
| Description |
A/MU-LAW, ADPCM CODEC, PQCC28 PLASTIC, LCC-28
Dual ADPCM Transcoder
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| File Size |
335.35K /
18 Page |
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it Online |
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意法半导
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| Part No. |
L6611DTR
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| OCR Text |
...voltage rails (+3.3v, +5v, 12v) generated by a main converter and of a supply line generated by an auxiliary converter. the typical application circuit is showed on the front page. the housekeeping's main function is to control and monitor ... |
| Description |
DIGITALLY PROGRAMMABLE SECONDARY HOUSEKEEPING CONTROLLER
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| File Size |
612.94K /
28 Page |
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it Online |
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