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				Cypress Semiconductor Corp.
Part No.	CY7C1214F CY7C1214F-100AC
OCR Text	...urst counter supporting Pentium interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed write * Asynchronous output enable * Supports 3.3V I/O level * Offered in JEDEC-standard 100-...
Description	1-Mb (32K x 32) Flow-Through Sync SRAM
File Size	286.23K / 15 Page	View it Online	Download Datasheet

				Alliance Semiconductor Corporation
Part No.	AS7C251MPFD32A AS7C251MPFD36A
OCR Text	....5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs Logic block diagram LBO CLK ADV ADSC ADSP A[19:0] 20 CLK CE CLR Q0 Burst logic Q1 2 2 D Q CE Address...
Description	(AS7C251MPFD32A / AS7C251MPFD36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
File Size	555.08K / 19 Page	View it Online	Download Datasheet

				Analog Device
Part No.	AN-555
OCR Text	...dual digital inputs, as well as interleaved DACs where data is alternately written from digital input Port 1 to either of the two DACs. Information on how to operate the evaluation board is included in this application note. However, for mo...
Description	Application Note
File Size	249.38K / 12 Page	View it Online	Download Datasheet

				Analog Devices
Part No.	AD9863 AD9863-50EB
OCR Text	...O data interface allows various interleaved or noninterleaved data transfers in half-duplex mode and interleaved data transfers in full-duplex mode Configurable through register programmability or optionally limited programmability through ...
Description	12-Bit Mixed-Signal Front-End (MxFE™ )Processor For Broadband Applications
File Size	686.39K / 40 Page	View it Online	Download Datasheet

				Alliance Semiconductor Corporation
Part No.	AS7C251MFT36A
OCR Text	...v core power supply ? linear or interleaved burst control ? snooze mode for reduced power-standby ? common data inputs and data outputs logic block diagram selection guide -75 -85 -10 units minimum cycle time 8.5 10 12 ns maximum clock acce...
Description	(AS7C251MFT32A / AS7C251MFT36A) 2.5V 1M x 32/36 Flow-through synchronous SRAM
File Size	550.46K / 19 Page	View it Online	Download Datasheet

				MOTOROLA[Motorola, Inc] Motorola, Inc. Motorola Mobility Holdings, Inc. MOTOROLA INC
Part No.	MCM69P536C MCM69P536CTQ4 MCM69P536CTQ4.5 MCM69P536CTQ4.5R MCM69P536CTQ4R MCM69P536CTQ5 MCM69P536CTQ5R MCM69P536CTQ6 MCM69P536CTQ6R MCM69P536CTQ7 MCM69P536CTQ7R
OCR Text	... sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) inpu...
Description	32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM 32K X 36 CACHE SRAM, 4.5 ns, PQFP100 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM 32K X 36 CACHE SRAM, 4 ns, PQFP100
File Size	210.55K / 12 Page	View it Online	Download Datasheet

				MOTOROLA[Motorola, Inc] Motorola Mobility Holdings, Inc.
Part No.	MCM69P618C MCM69P618CTQ4 MCM69P618CTQ4.5 MCM69P618CTQ4.5R MCM69P618CTQ4R MCM69P618CTQ5 MCM69P618CTQ5R MCM69P618CTQ6 MCM69P618CTQ6R MCM69P618CTQ7 MCM69P618CTQ7R
OCR Text	... sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self-timed and initiated by the rising edge of the clock (K) input. T...
Description	64K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM 64K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM 64K X 18 CACHE SRAM, 4 ns, PQFP100 64K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM 64K X 18 CACHE SRAM, PQFP100
File Size	204.87K / 12 Page	View it Online	Download Datasheet

				MOTOROLA[Motorola, Inc]
Part No.	MCM69P735 MCM69P735ZP2.5 MCM69P735ZP2.5R MCM69P735ZP3 MCM69P735ZP3.5 MCM69P735ZP3.5R MCM69P735ZP3R
OCR Text	... sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) inpu...
Description	128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
File Size	183.41K / 16 Page	View it Online	Download Datasheet

				MOTOROLA[Motorola, Inc]
Part No.	MCM69P736 MCM69P736ZP4 MCM69P736ZP4R
OCR Text	... sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) inpu...
Description	128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
File Size	180.78K / 16 Page	View it Online	Download Datasheet

For interleaved Found Datasheets File :: 4029 Search Time::3.078ms
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