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ONSEMI[ON Semiconductor]
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| Part No. |
NB100LVEP221FAR2 NB100LVEP221 NB100LVEP221FA NB100LVEP221D NB100LVEP221/D
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| OCR Text |
...receive hstl signal levels. The lvpecl input signals can be either differential configuration or single-ended (if the VBB output is used). The LVEP221 specifically guarantees low output-to-output skew. Optimal design, layout, and processing... |
| Description |
2.5V/3.3V 1:20 Differential hstl/ECL/PECL Clock Driver 2.5V/3.3V:20差分hstl / ECL / PECL的时钟驱动器
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| File Size |
94.29K /
10 Page |
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ONSEMI[ON Semiconductor]
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| Part No. |
NB100LVEP91DW NB100LVEP91 NB100LVEP91MNR2 NB100LVEP91DWR2 NB100LVEP91MN NB100LVEP91-D
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| OCR Text |
... translator. The device accepts lvpecl, LVTTL, LVCMOS, hstl, CML or LVDS signals, and translates them to differential NECL output signals (-2.5 V / -3.3 V / -5 V). To accomplish the level translation the LVEP91 requires three power rails. T... |
| Description |
2.5V / 3.3V AnyLevel Positive Input to -2.5V / -3.3V / -5V NECL Output Translator 2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator From old datasheet system
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| File Size |
76.20K /
8 Page |
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ONSEMI[ON Semiconductor]
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| Part No. |
NB6L23906 NB6L239MNR2G NB6L239 NB6L239MN NB6L239MNG NB6L239MNR2
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| OCR Text |
lvpecl OUT /1/2/4/8, /2/4/8/16 Clock Divider
Description http://onsemi.com
The NB6L239 is a high-speed, low skew clock divider with two ...hstl EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS Rise/Fall Time 65 ps Typical < 10 ps Typica... |
| Description |
2.5V / 3.3V Any Differential Clock IN to Differential lvpecl OUT /1/2/4/8, /2/4/8/16 Clock Divider
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| File Size |
101.80K /
13 Page |
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Download Datasheet
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MICREL[Micrel Semiconductor]
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| Part No. |
SY89538L06 SY89538LHGTR SY89538L SY89538LHG
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| OCR Text |
lvpecl and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay
General Description
The SY89538L i...hstl, and SSTL. RFCK requires an external termination. See "Input Interface" and "Input Termination"... |
| Description |
3.3V, Precision lvpecl and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay
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| File Size |
627.79K /
23 Page |
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Download Datasheet
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Price and Availability
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