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CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY7C109D-10ZXC
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OCR Text |
...o the device is accomplished by taking chip enable one (ce 1 ) and write enable (we ) inputs low and chip enable two (ce 2 ) input high. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the a... |
Description |
128K X 8 STANDARD SRAM, 10 ns, PDSO32
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File Size |
241.93K /
9 Page |
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it Online |
Download Datasheet
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY7C1021DV33-10ZXC
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OCR Text |
...o the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 t... |
Description |
64K X 16 STANDARD SRAM, 10 ns, PDSO44
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File Size |
250.12K /
11 Page |
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it Online |
Download Datasheet
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY62137CV33LL-55BVIT
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OCR Text |
...o the device is accomplished by taking chip enable ( ce ) and write enable ( we ) inputs low. if byte low enable ( ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins ... |
Description |
128K X 16 STANDARD SRAM, 55 ns, PBGA48
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File Size |
595.42K /
13 Page |
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it Online |
Download Datasheet
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY62136CV33LL-55BAIT CY62136CV30LL-55BAIT CY62136CV33LL-70BAIT
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OCR Text |
...o the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 t... |
Description |
128K X 16 STANDARD SRAM, 55 ns, PBGA48 128K X 16 STANDARD SRAM, 70 ns, PBGA48
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File Size |
227.24K /
13 Page |
View
it Online |
Download Datasheet
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY62127DV30LL-45ZXIT
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OCR Text |
...o the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 t... |
Description |
64K X 16 STANDARD SRAM, 45 ns, PDSO44
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File Size |
527.75K /
11 Page |
View
it Online |
Download Datasheet
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY62146CV33LL-70BAI CY62146CV25LL-70BAI
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OCR Text |
...o the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 t... |
Description |
256K X 16 STANDARD SRAM, 70 ns, PBGA48
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File Size |
176.77K /
11 Page |
View
it Online |
Download Datasheet
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Price and Availability
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