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LM139 A1182 PXF4222 28B28S LV7150V HN9C05FT M1MA151A MPS65
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    CYPRESS SEMICONDUCTOR CORP
Part No. CY7C109D-10ZXC
OCR Text ...o the device is accomplished by taking chip enable one (ce 1 ) and write enable (we ) inputs low and chip enable two (ce 2 ) input high. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the a...
Description 128K X 8 STANDARD SRAM, 10 ns, PDSO32

File Size 241.93K  /  9 Page

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    CYPRESS SEMICONDUCTOR CORP
Part No. CY7C1021DV33-10ZXC
OCR Text ...o the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 t...
Description 64K X 16 STANDARD SRAM, 10 ns, PDSO44

File Size 250.12K  /  11 Page

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    CYPRESS SEMICONDUCTOR CORP
Part No. CY62137CV33LL-55BVIT
OCR Text ...o the device is accomplished by taking chip enable ( ce ) and write enable ( we ) inputs low. if byte low enable ( ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins ...
Description 128K X 16 STANDARD SRAM, 55 ns, PBGA48

File Size 595.42K  /  13 Page

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    CYPRESS SEMICONDUCTOR CORP
Part No. CY62136CV33LL-55BAIT CY62136CV30LL-55BAIT CY62136CV33LL-70BAIT
OCR Text ...o the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 t...
Description 128K X 16 STANDARD SRAM, 55 ns, PBGA48
128K X 16 STANDARD SRAM, 70 ns, PBGA48

File Size 227.24K  /  13 Page

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    CYPRESS SEMICONDUCTOR CORP
Part No. CY62127DV30LL-45ZXIT
OCR Text ...o the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 t...
Description 64K X 16 STANDARD SRAM, 45 ns, PDSO44

File Size 527.75K  /  11 Page

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    M95128-BN5

STMICROELECTRONICS
Part No. M95128-BN5
OCR Text ...o remove the hold condition (by taking hold high) and to select the memory (by taking s low). operations all instructions, addresses and data are shifted serially in and out of the chip. the most significant bit is presented first, with t...
Description 16K X 8 SPI BUS SERIAL EEPROM, PDIP8

File Size 179.19K  /  21 Page

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    X25128 X25128P X25128P-2.7 X25128PI X25128PI-2.7 X25128PM X25128PM-2.7 X25128S X25128S14 X25128S14-2.7 X25128S14I X25128

Intersil, Corp.
IC MICROSYSTEMS Sdn. Bhd.
XICOR[Xicor Inc.]
Part No. X25128 X25128P X25128P-2.7 X25128PI X25128PI-2.7 X25128PM X25128PM-2.7 X25128S X25128S14 X25128S14-2.7 X25128S14I X25128S14I-2.7 X25128S14M X25128S14M-2.7 X25128S-2.7 X25128SI X25128SI-2.7 X25128SM X25128SM-2.7
OCR Text ...read operation is terminated by taking CS high. Refer to the read E2PROM array operation sequence illustrated in Figure 1. To read the status register the CS line is first pulled low to select the device followed by the 8-bit instruction. A...
Description SPI Serial E 2 PROM with Block Lock TM Protection SPI串行e2座门锁TM保护胎膜早破
IND 10UH 20%.3.3A 0.0267 OHMS

File Size 75.40K  /  15 Page

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    X25138 X25138P2.5 X25138PI2.5 X25138PI-V X25138PT2.5 X25138PT-V X25138P-V X25138S142.5 X25138S14I2.5 X25138S14I-V X25138

XICOR[Xicor Inc.]
Part No. X25138 X25138P2.5 X25138PI2.5 X25138PI-V X25138PT2.5 X25138PT-V X25138P-V X25138S142.5 X25138S14I2.5 X25138S14I-V X25138S14T2.5 X25138S14T-V X25138S14-V X25138S82.5 X25138S8I2.5 X25138S8I-V X25138S8T2.5 X25138S8T-V X25138S8-V X25138V82.5 X25138V8I2.5 X25138V8I-V X25138V8T2.5 X25138V8T-V X25138V8-V X25138Z2.5 X25138ZI2.5 X25138ZI-V X25138ZT2.5 X25138ZT-V X25138Z-V
OCR Text ...read operation is terminated by taking CS HIGH. Refer to the read E2PROM array operation sequence illustrated in Figure 1. To read the status register the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instructi...
Description 5MHz SPI Serial E2PROM with Block Lock PROTECTION

File Size 88.45K  /  18 Page

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    CYPRESS SEMICONDUCTOR CORP
Part No. CY62146CV33LL-70BAI CY62146CV25LL-70BAI
OCR Text ...o the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 t...
Description 256K X 16 STANDARD SRAM, 70 ns, PBGA48

File Size 176.77K  /  11 Page

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    X25163 X25163S14 X25163S14-1.8 X25163S14-2.7 X25163S14I X25163S14I-1.8 X25163S14I-2.7 X25163S8 X25163S8-1.8 X25163S8-2.7

Omron Electronics LLC Industrial Automation
XICOR[Xicor Inc.]
Part No. X25163 X25163S14 X25163S14-1.8 X25163S14-2.7 X25163S14I X25163S14I-1.8 X25163S14I-2.7 X25163S8 X25163S8-1.8 X25163S8-2.7 X25163S8I X25163S8I-1.8 X25163S8I-2.7 X25163V14 X25323 X25323S14 X25323S14-1.8 X25323S14-2.7 X25323S14I X25323S14I-1.8 X25323S14I-2.7 X25323S8 X25323S8-1.8 X25323S8-2.7 X25323S8I X25323S8I-1.8 X25323S8I-2.7 X25323V14 X25323V14-1.8 X25323V14-2.7 X25323V14I X25323V14I-1.8 X25323V14I-2.7 X25325 X25325S14 X25325S14-1.8 X25325S14-2.7 X25325S14I X25325S14I-1.8 X25325S14I-2.7 X25325S8 X25325S8-1.8 X25325S8-2.7 X25325S8I X25325S8I-1.8 X25325S8I-2.7 X25325V14 X25325V14-1.8 X25325V14-2.7 X25325V14I X25325V14I-1.8 X25325V14I-2.7 X25643 X25643S14 X25643S14-1.8 X25643S14-2.7 X25643S14I X25643S14I-1.8 X25643S14I-2.7 X25643S8 X25643S8-1.8 X25643S8-2.7 X25643S8I X25643S8I-1.8 X25643S8I-2.7 X25643V14 X25643V14-1.8 X25643V14-2.7 X25643V14I X25643V14I-1.8 X25643V14I-2.7 X25645 X25645S14 X25645S14-1.8 X25645S14-2.7 X25645S14I X25645S14I-1.8 X25645S14I-2.7 X25165 X25165S14 X25165S14-1.8 X25165S14-2.7 X25165S14I X25165S14I-1.8 X25165S14I-2.7 X25165S8 X25165S8-1.8 X25165S8-2.7 X25165S8I X25165S8I-1.8 X25165S8I-2.7 X25165V14 X25165V14-1.8 X25165V14-2.7 X25165V14I X25165V14I-1.8 X25165V1
OCR Text ...read operation is terminated by taking CS high. Refer to the Read E2PROM Array Sequence (Figure 1). To read the Status Register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opc...
Description Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM 可编程看门狗定时
RACKMOUNT ENHANCED 8 PORTRJ45 TERMINAL SERVER
Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM

File Size 74.33K  /  16 Page

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