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Integrated Device Technology, Inc.
ICS
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| Part No. |
ICS8735-31I ICS8735I-31 ICS8735AYI-31LF ICS8735AYI-31T
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| OCR Text |
...tput divider values in Table 3. LVCMOS interface levels. Pulldown Determines output divider values in Table 3. LVCMOS interface levels. Pull...to go low and the inver ted outputs (nQx) to Pulldown go high. When logic LOW, the internal dividers... |
| Description |
8735 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32
8735 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-32
Low Skew, Low Jitter 1-to-5, Differential-to-Zero Delay LVPECL Clock Generator (P)
From old datasheet system
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| File Size |
172.74K /
16 Page |
 View
it Online |
Download Datasheet
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ICS
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| Part No. |
ICS8735-31
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| OCR Text |
...tput divider values in Table 3. LVCMOS interface levels. Pulldown Determines output divider values in Table 3. LVCMOS interface levels. Pull...to go low and the inver ted outputs (nQx) to Pulldown go high. When logic LOW, the internal dividers... |
| Description |
From old datasheet system
Low Skew, Low Jitter 1-to-5, Differential-to-Zero Delay LVPECL Clock Generator (P)
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| File Size |
181.09K /
16 Page |
View
it Online |
Download Datasheet |
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ICS
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| Part No. |
ICS87354I
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| OCR Text |
... any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input * Part-to-part skew: 300ps (maximum) * Propagation delay: 2.1ns (maximum) * LVPECL mode operating voltage supply range: VCC = 3.0V to 3.46... |
| Description |
From old datasheet system
Divide-by-4, 5 Clock Generator. Industrial Temperature.
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| File Size |
152.16K /
12 Page |
View
it Online |
Download Datasheet |
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