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Part No. |
MT41K256M4JP-125G
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OCR Text |
... read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge com- mand determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10... |
Description |
256M X 4 DDR DRAM, PBGA78
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File Size |
446.14K /
21 Page |
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it Online |
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NXP Semiconductors
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Part No. |
LPC1853JET256 LPC1857FET256 LPC1837JET256 LPC1833FET256 LPC1833JBD144 LPC1833JET100 LPC1833JET256 LPC1837FET256 LPC1837JBD144 LPC1837JET100 LPC1825JBD144 LPC1822JET100 LPC1823JET100 LPC1823JBD144 LPC1853JBD208 LPC1857JET256 LPC1817JET100 LPC1827JET100 LPC1857JBD208
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OCR Text |
...e drivers. ? 64 bit+ 256 bit of one-time programmable (otp) memory for general-purpose use. ? clock generation unit ? crystal oscillator wi...bank a flash bank b total sram lcd ethernet usb0 (host, device, otg) usb1 (host, device)/ ulpi inter... |
Description |
512kB flash, 136kB SRAM, Ethernet, LCD, LBGA256 package 1024kB flash, 136kB SRAM, Ethernet, LCD, LBGA256 package 1024kB flash, 136kB SRAM, Ethernet, LBGA256 package 512kB flash, 136kB SRAM, Ethernet, LBGA256 package 512kB flash, 136kB SRAM, Ethernet, LQFP144 package 512kB flash, 136kB SRAM, Ethernet, TFBGA100 package 1024kB flash, 136kB SRAM, Ethernet, LQFP144 package 1024kB flash, 136kB SRAM, Ethernet, TFBGA100 package 768kB flash, 136kB SRAM, LQFP144 package 512kB flash, 104kB SRAM, TFBGA100 package 512kB flash, 104kB SRAM, LQFP144 package 512kB flash, 136kB SRAM, Ethernet, LCD, LQFP208 package 1024kB flash, 136kB SRAM, TFBGA100 package 1024kB flash, 136kB SRAM, Ethernet, LCD, LQFP208 package
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File Size |
2,714.94K /
148 Page |
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it Online |
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Nanya Techology
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Part No. |
NT5DS32M8BW
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OCR Text |
...ists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-c...bank and row to be accessed. the address bits registered coincident with the read or write command... |
Description |
(NT5DSxxMxBx) 256Mb DDR SDRAM
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File Size |
1,959.62K /
80 Page |
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it Online |
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Part No. |
M366S0824CT0-C1L M366S0824CT0-C1H
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OCR Text |
... cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. cke should be enabled 1clk+...bank select address selects bank to be activated during row address latch time. selects bank for rea... |
Description |
8M X 64 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
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File Size |
137.24K /
9 Page |
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it Online |
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HYNIX SEMICONDUCTOR INC
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Part No. |
HMT41GV7BMR4C-H9
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OCR Text |
...r read/write commands to select one location out of the mem- ory array in the respective bank. a10 is sampled during a precharge command to deter- mine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only on... |
Description |
DDR DRAM MODULE, DMA240
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File Size |
1,060.21K /
61 Page |
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it Online |
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Part No. |
PSX96B-PQ160
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OCR Text |
...entical and predictable delays one-to-one, one-to-many and many-to-one connections ? rapidconnect? parallel interface for fast, incremental switching of buses in 12.5 ns bank switching for instantaneous reconfiguration of entire switch ... |
Description |
LOADABLE PLD, PQFP160
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File Size |
348.07K /
53 Page |
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it Online |
Download Datasheet |
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Price and Availability
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