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  PALCE26V12H-20PI 4 Datasheet PDF File

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Part No. CAT64LC20J CAT64LC40J CAT64LC10PI CAT64LC40SA CAT64LC40SI CAT64LC20SI CAT64LC20JI CAT64LC20PI
Description 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write
36-Mbit DDR-II SRAM 2-Word Burst Architecture
9-Mbit QDR- II™ SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture
36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture
SPI Serial EEPROM
4-Mbit (128K x 36) Pipelined Sync SRAM
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
File Size 87.91K  /  9 Page

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