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Motorola
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| Part No. |
HCS12HFAMILYPP
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| OCR Text |
...ram, 4k bytes of eeprom, one or two asynchronous serial communications interfaces (sci), a serial peripheral interface (spi), an iic-bus int...pll circuit allows power consumption and performance to be adjusted to suit operational requirements... |
| Description |
HCS12 H-Family Product Proposal
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| File Size |
350.49K /
13 Page |
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Zarlink Semiconductor Inc.
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| Part No. |
ZL30409/DDB ZL30409/DDA
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| OCR Text |
...? accepts reference inputs from two independent sources ? jtag boundary scan applications ? synchronization and timing control for multitru...pll is frequency locked to the input reference. 19 c2o clock 2.048mhz (cmos output). this outpu... |
| Description |
T1/E1 System Synchronizer with Stratum 3 Holdover
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| File Size |
290.90K /
32 Page |
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it Online |
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飞思卡尔半导体(中国)有限公司
椋???″????浣?涓??)??????
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| Part No. |
MCF5251 MCF5251CEVM140
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| OCR Text |
...rsion 2 (c f2) core consists of two independe nt, decoupled pipe line structures to maximize performance while minim izing core size. the i...pll sections of the mcf5251, reducing the number of external components required and allowing ope... |
| Description |
ColdFire Processor
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| File Size |
284.26K /
32 Page |
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it Online |
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Motorola, Inc.
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| Part No. |
MC88915FN70PLCC MC88915FN55PLCC
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| OCR Text |
...ided for low frequency testing. two selectable clock inputs for test or redundancy purposes
pll_en gnd q1 v cc q0 gnd freq_sel lock gnd q2 v cc q3 gnd q/2 rc1 gnd(an) v cc (an) sync[1] sync[0] ref_sel feedback 2x_q rst v cc v cc q4 ... |
| Description |
Low Skew CMOS PLL Clock Driver
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| File Size |
150.18K /
13 Page |
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it Online |
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Kawasaki
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| Part No. |
KL5KUSB107
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| OCR Text |
...which may occupy another one or two words. several special ? short immediate? instructions are available, so that certain frequently used o...pll clock generator the pll circuitry is provided to generate the internal 48mhz clock. this circui... |
| Description |
USB Combo - Serial & Parallel
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| File Size |
169.37K /
8 Page |
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it Online |
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