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LN349GP TDA1523 CR6CM 103029 SSM2118T TCD965 ST33F768 EBV250
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    SILICON STORAGE TECHNOLOGY INC
Part No. SST38VF6404-90-4C-EKE SST38VF6401-90-4C-EKE SST38VF6401-90-4C-B3KE SST38VF6404-90-4I-B3KE SST38VF6404-90-4C-B3KE
OCR Text ...rst#) ? fast read and page read access times: ? 90 ns read access time ? 25 ns page read access times - 4-word page read buffer ? latched ad...edge of we# or ce#, which- ever occurs last. the data bus is latched on the rising edge of we# or c...
Description 4M X 16 FLASH 2.7V PROM, 90 ns, PDSO48
4M X 16 FLASH 2.7V PROM, 90 ns, PBGA48

File Size 1,272.91K  /  55 Page

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    CY7C1325H-133AXI

Cypress Semiconductor
Part No. CY7C1325H-133AXI
OCR Text ...rovide high performance 2-1-1-1 access rate user selectable burst counter supporting intel pentium interleaved or linear burst sequences s...edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, add...
Description 4-Mbit (256 K × 18) Flow-Through Sync SRAM

File Size 587.04K  /  21 Page

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    71V3558S200PFG

Integrated Device Technology
Part No. 71V3558S200PFG
OCR Text ...mhz (x18) (3.2 ns clock-to-data access) supports high performance system speed - 166 mhz (x36) (3.5 ns clock-to-data access) zbt t...edge triggered address, data, and control signal registers for fully pipelined applications 4-w...
Description 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

File Size 644.98K  /  28 Page

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    IS42S16400F-7TL-TR IC42S16400F-7TL

Integrated Silicon Solution, Inc
Part No. IS42S16400F-7TL-TR IC42S16400F-7TL
OCR Text ...ernal bank for hiding row access/precharge ? single 3.3v power supply ? lvttl interface ? programmable burst length C (1, 2...edge of the clock input. 1 meg bits x 16 bits x 4 banks (64-mbit) synchronous dynamic ram march 2...
Description 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

File Size 649.85K  /  55 Page

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    OKI Semiconductor
Part No. MS82V16520
OCR Text access memory organized as 256 k words 32 bits 2 banks. this device can operate up to 143 mhz by using synchronous interface. in add...edge of system clock ? auto precharge and controlled precharge ? internal pipelined operation: colu...
Description Synchronous Graphics RAM

File Size 877.18K  /  67 Page

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    MOTOROLA INC
Part No. MCM64Z916ZP100R MCM64Z834ZP100R
OCR Text ...ble ? mcm64z834 / 916143 = 4 ns access / 7 ns cycle (143 mhz) mcm64z834 / 916133 = 4.2 ns access / 7.5 ns cycle (133 mhz) mcm64z834 / 916100...edge rate variations on correlation between data sheet parameters and actual system performance, fsr...
Description 512K X 18 ZBT SRAM, 5 ns, PBGA119
256K X 36 ZBT SRAM, 5 ns, PBGA119

File Size 360.86K  /  32 Page

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    FEDS82V48540-01

OKI electronic componets
Part No. FEDS82V48540-01
OCR Text ...ock synchronous dynamic rand om access memory. in addition to the conventional random read/write access function, the ms 82v48540 provides...edge. cs disables or enables device operation by asserting or deactivating all inputs except clk,...
Description 393,216-Word × 32-Bit × 4-Bank FIFO-SGRAM

File Size 1,411.15K  /  44 Page

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    XILINX INC
Part No. XC18V04VQ44C0799 XC18V02VQ44C0799
OCR Text ...k that drives the prom. a short access time after ce and oe are enabled, data is available on the prom data (d0) pin that is connected to t...edge. the fpga generates the appropriate num- ber of clock pulses to complete the configuration. whe...
Description 512K X 8 CONFIGURATION MEMORY, 20 ns, PQFP44
256K X 8 CONFIGURATION MEMORY, 20 ns, PQFP44

File Size 408.50K  /  26 Page

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    LAPIS SEMICONDUCTOR CO LTD
Part No. MSM56V16160D-12TS-K
OCR Text ... dynamic ram preliminary family access time (max.) msm56v16160d-10 msm56v16160d-12 msm56v16160dh-15 max. frequency 100 mhz 83 mhz 66 mhz 9 n...edge. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, syst...
Description 1M X 16 SYNCHRONOUS DRAM, 10 ns, PDSO50

File Size 376.49K  /  31 Page

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    AD7814 AD7814ARM AD7814ART

Analog Devices, Inc.
AD[Analog Devices]
Part No. AD7814 AD7814ARM AD7814ART
OCR Text ...ewidth SCLK Low Pulsewidth Data access Time After SCLK Falling edge Data Setup Time Prior to SCLK Rising edge Data Hold Time After SCLK Rising edge CS to SCLK Hold Time CS to DOUT High Impedance NOTES 1 Guaranteed by design and character...
Description 10-Bit Digital Temperature Sensor in 6-Lead SOT-23

File Size 99.38K  /  8 Page

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