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Cypress Semiconductor, Corp.
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Part No. |
CY7C1263V18-300BZI
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OCR Text |
... buffers available in 165-ball fbga package (15 x 17 x 1.4 mm) offered in both pb-free and non pb-free packages jtag 1149.1 compatible test access port delay lock loop (dll) for accurate data placement configurations with read cycle lat... |
Description |
36-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 18 QDR SRAM, 0.45 ns, PBGA165
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File Size |
434.14K /
29 Page |
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Cypress Semiconductor, Corp.
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Part No. |
CY7C1380F-200BGXI CY7C1380F-167BGXI CY7C1380D-250BZXI CY7C1380F-250BGC
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OCR Text |
...-free and non pb-free 165-ball fbga package; cy7c1380f/cy7c1382f is available in jedec-standard pb-free 100-pin tqfp, pb-free and non pb-free 119-ball bga and 165-ball fbga package ieee 1149.1 jtag-compatible boundary scan zz sleep mo... |
Description |
18-Mbit (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 3 ns, PBGA119 18-Mbit (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 3.4 ns, PBGA119 18-Mbit (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 2.6 ns, PBGA165 18-Mbit (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 2.6 ns, PBGA119
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File Size |
854.97K /
34 Page |
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it Online |
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Cypress Semiconductor, Corp.
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Part No. |
CY7C1380DV25-250BZXI CY7C1380DV25-200BZC CY7C1380DV25-200AXI
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OCR Text |
...-free and non pb-free 165-ball fbga package. cy7c1380fv25/cy7c1382fv25 available in pb-free and non pb-free 119-ball bga package ? ieee 1149.1 jtag-compatible boundary scan ? zz sleep mode option functional description [1] the cy7c1380d... |
Description |
18-Mbit (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 2.6 ns, PBGA165 18-Mbit (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 3 ns, PBGA165 18-Mbit (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 3 ns, PQFP100
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File Size |
930.63K /
29 Page |
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it Online |
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Cypress Semiconductor, Corp. CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY7C1543KV18-400BZC CY7C1545KV18-450BZXI
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OCR Text |
... buffers available in 165-ball fbga package (13 x 15 x 1.4 mm) offered in both pb-free and non pb-free packages jtag 1149.1 compatible test access port phase-locked loop (pll) for accurate data placement configurations with read cycle l... |
Description |
Sync SRAM; Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 QDR SRAM, 0.45 ns, PBGA165 2M X 36 QDR SRAM, 0.45 ns, PBGA165
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File Size |
562.79K /
28 Page |
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it Online |
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