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pll-ii Datasheet PDF File

For pll-ii Found Datasheets File :: 2683 Search Time::1.718ms
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				ETC[ETC]
Part No.	QL8050 QL8150 QL8250 QL8025 QL8325
OCR Text	...VTTL, LVCMOS, LVCMOS18, PCI, PLL Embedded RAM Blocks Embeded Computational Units PLL GTL+, SSTL2, and SSTL3 Independent I/O Ba...II is fabricated on a 0.18 , six layer metal CMOS process. The core voltage is 1.8 V Vcc supply and ...
Description	LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
File Size	442.48K / 49 Page	View it Online	Download Datasheet

				Altera Corporation
Part No.	HC1S60
OCR Text	...h, clock switchover, real-time pll reconfiguration, advanced multiplication, and phase shifting supports numerous single-ended and differ...ii i/o pin counts include one additional pin, pllena , which is not a general-purpose i/o pin. pl...
Description	HardCopy Stratix Device Family
File Size	1,170.40K / 110 Page	View it Online	Download Datasheet

				Asahi Kasei Microsystems
Part No.	AK4584
OCR Text	...EIAJ CP1201 * Low Jitter Analog PLL * PLL Lock Range: 32k 192kHz * Clock Source: PLL or X'tal * 4 Channels Receiver Inputs * Detect Functio...iI"(R)iIUOeUnB *"(R)iOE (AVSS, DVSS, PVSS=0V; Note 1) Parameter Power Supplies Analog (No...
Description	24BIT 96KHZ AUDIO CODEC WITH DIT/DIR
File Size	311.84K / 53 Page	View it Online	Download Datasheet

				CYPRESS SEMICONDUCTOR CORP
Part No.	CY7C1522KV18-250BZI CY7C1529KV18-300BZXI CY7C1529KV18-167BZXC
OCR Text	...access port phase locked loop (pll) for accurate data placement configurations cy7c1522kv18 ? 8m x 8 cy7c1529kv18 ? 8m x 9 cy7c1523kv18 ? 4...ii sio (double data rate separate i/o) architecture. the ddr ii sio consists of two separate ports: ...
Description	8M X 8 DDR SRAM, 0.45 ns, PBGA165 8M X 9 DDR SRAM, 0.45 ns, PBGA165 8M X 9 DDR SRAM, 0.5 ns, PBGA165
File Size	591.02K / 32 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1315KV18 CY7C1315KV18-250BZC CY7C1315KV18-250BZXC CY7C1315KV18-250BZXI CY7C1315KV18-300BZC CY7C1313KV18 CY7C1313KV18-250BZC CY7C1313KV18-250BZI CY7C1311KV18 CY7C1313KV18-250BZXI
OCR Text	...9.1 compatible test access port PLL for accurate data placement Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV...II architecture. QDR II architecture consists of two separate ports: the read port and the write por...
Description	18-Mbit QDR? II SRAM Four-Word Burst Architecture
File Size	622.94K / 33 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp.
Part No.	CY7C1518KV18-300BZXC
OCR Text	...access port phase-locked loop (pll) for accurate data placement configurations cy7c1516kv18 ? 8m x 8 cy7c1527kv18 ? 8m x 9 cy7c1518kv18 ? 4...ii architectu re. the ddr ii consists of an sram core with advanced synchronous peripheral circuitry...
Description	72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
File Size	973.05K / 33 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CYP15G0401TB-BGXI CYP15G0401TB-BGI CYP15G0401TB-BGC CYP15G0401TB-BGXC
OCR Text	...h ? internal phase-locked loop (pll) with no external pll components ? dual differential pecl-compatible serial outputs per channel ? sour...ii? transmitter is a point-to-point or point-to-mult ipoint communications building block allowing t...
Description	Quad HOTLink II?/a> Transmitter
File Size	288.58K / 30 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1265KV18 CY7C1276KV18 CY7C1265KV18-550BZC CY7C1265KV18-400BZC CY7C1265KV18-400BZXC CY7C1265KV18-450BZXC CY7C1263KV18-400BZC CY7C1263KV18-400BZI CY7C1263KV18-500BZXC CY7C1263KV18-550BZI CY7C1261KV18 CY7C1263KV18-550BZXC CY7C1265KV18-550BZXC
OCR Text	... access port Phase-locked loop (PLL) for accurate data placement Description Functional Description The CY7C1261KV18, CY7C1276KV...II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate port...
Description	36-Mbit QDR? II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
File Size	658.28K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1245KV18 CY7C1243KV18 CY7C1243KV18-400BZC CY7C1241KV18 CY7C1243KV18-450BZC CY7C1245KV18-450BZC CY7C1245KV18-400BZC CY7C1245KV18-400BZXC CY7C1256KV18
OCR Text	... access port Phase-locked loop (PLL) for accurate data placement Description Functional Description The CY7C1241KV18, CY7C1256KV...II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate port...
Description	36-Mbit QDR? II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
File Size	630.78K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1268XV18-600BZXC CY7C1270XV18-600BZXC CY7C1268XV18-633BZXC
OCR Text	...access port phase-locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles: cy7c1268xv18 ? 2 m 1...ii+ architecture. the ddr ii+ consists of an sram core with advanced synchronous peripheral circuitr...
Description	36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
File Size	669.28K / 28 Page	View it Online	Download Datasheet

For pll-ii Found Datasheets File :: 2683 Search Time::1.718ms
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