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IDT[Integrated Device Technology]
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| Part No. |
IDT72V70210DA IDT72V70210 IDT72V70210BC
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| OCR Text |
... useful in compensating for the skew between clocks. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +4 master clock (CLK) periods forward w... |
| Description |
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
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| File Size |
115.09K /
19 Page |
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it Online |
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IDT[Integrated Device Technology]
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| Part No. |
IDT72V73250DA IDT72V73250 IDT72V73250BB
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| OCR Text |
... useful in compensating for the skew between input streams. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5 master clock (C32i) periods... |
| Description |
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
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| File Size |
169.55K /
24 Page |
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it Online |
Download Datasheet |
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IDT[Integrated Device Technology]
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| Part No. |
IDT72V73260DA IDT72V7326 IDT72V73260 IDT72V73260BB
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| OCR Text |
... useful in compensating for the skew between input streams. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5 master clock (C32i) periods... |
| Description |
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 X 16,384
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| File Size |
187.19K /
26 Page |
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it Online |
Download Datasheet |
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skew-compensating Found Datasheets File :: 34 Search Time::1.454ms
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