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DSEI2X61 E000421 TLPGE MC33163 6821M 3362R203 6821M 56163
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  18 1m Datasheet PDF File

For 18 1m Found Datasheets File :: 14334    Search Time::5.656ms    
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    CY7C1418AV18-167BZI CY7C1418AV18-167BZXC CY7C1418AV18-167BZXI CY7C1418AV18-200BZI CY7C1418AV18-200BZXC CY7C1418AV18-278B

Cypress Semiconductor
Part No. CY7C1418AV18-167BZI CY7C1418AV18-167BZXC CY7C1418AV18-167BZXI CY7C1418AV18-200BZI CY7C1418AV18-200BZXC CY7C1418AV18-278BZC CY7C1418AV18-278BZXC CY7C1418AV18-250BZXI CY7C1418AV18-250BZI CY7C1418AV18-278BZXI
OCR Text ...t density (4M x 8, 4M x 9, 2M x 18, 1m x 36) * 300-MHz clock for high bandwidth * 2-Word burst for reducing address bus frequency * Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz * Two input clocks (K and K) for p...
Description 36-Mbit DDR-II SRAM 2-Word Burst Architecture

File Size 501.10K  /  28 Page

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    CY7C1166V18-300BZXC CY7C1166V18-333BZXC

Cypress Semiconductor
Part No. CY7C1166V18-300BZXC CY7C1166V18-333BZXC
OCR Text 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Functional Description The CY7C1166V18, CY7C117...1m x 18, 512K x 36) 300 MHz to 400 MHz clock for high bandwidth 2-Word burst for reducing address bu...
Description 18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

File Size 1,019.93K  /  27 Page

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    CY7C1241V18-300BZXC CY7C1256V18 CY7C1256V18-300BZC CY7C1256V18-300BZI CY7C1256V18-300BZXC CY7C1256V18-300BZXI CY7C1241V1

Cypress Semiconductor
Part No. CY7C1241V18-300BZXC CY7C1256V18 CY7C1256V18-300BZC CY7C1256V18-300BZI CY7C1256V18-300BZXC CY7C1256V18-300BZXI CY7C1241V18-300BZI CY7C1245V18-300BZI CY7C1243V18-300BZI CY7C1243V18-300BZC CY7C1241V18-300BZC CY7C1245V18-300BZC CY7C1245V18-300BZXC CY7C1245V18-300BZXI
OCR Text ...18), 9-bit words (CY7C1256V18), 18-bit words (CY7C1243V18), or 36-bit words (CY7C1245V18), that burst sequentially into or out of the device...1m x 36 Selection Guide 375 MHz Maximum Operating Frequency Maximum Operating Current 375 1240 3...
Description 36-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
36-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
36-Mbit QDR?II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

File Size 1,101.30K  /  28 Page

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    CY7C1486V33-167BGC CY7C1486V33-167BGI CY7C1486V33-167BGXC CY7C1486V33-167BGXI CY7C1486V33-200BGC CY7C1486V33-200BGI CY7C

Cypress Semiconductor
Part No. CY7C1486V33-167BGC CY7C1486V33-167BGI CY7C1486V33-167BGXC CY7C1486V33-167BGXI CY7C1486V33-200BGC CY7C1486V33-200BGI CY7C1486V33-200BGXC CY7C1486V33-200BGXI CY7C1486V33-250BGC CY7C1486V33-250BGI CY7C1486V33-250BGXC CY7C1486V33-250BGXI CY7C1482V33-250BZI CY7C1482V33-250BZXI CY7C1480V33-200AXI CY7C1480V33-200BZI CY7C1480V33-200BZXI
OCR Text 18/1m x 72) Pipelined Sync SRAM Features * * * * * * Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 167 MHz Registered inputs and outputs for pipelined operation 3.3V core power supply 2.5V/3.3V I/O operatio...
Description 72-Mbit (2M x 36/4M x 18/1m x 72) Pipelined Sync SRAM

File Size 1,077.83K  /  32 Page

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    ST7533

Sitronix Technology Co., Ltd.
Part No. ST7533
OCR Text ...6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PIN...1m It is recommended to set an optimum resistance value R4 taking the liquid Figure 15 * 1. Because ...
Description 33 x 96 Dot Matrix LCD Controller/Driver

File Size 583.40K  /  60 Page

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    NCS2566 NCS2566DTBR2G

ON Semiconductor
Part No. NCS2566 NCS2566DTBR2G
OCR Text ... SD IN1 1 20 SD OUT1 19 SD OUT2 18 SD OUT3 17 GND 16 GND 15 SD/HD EN 14 SD/HD OUT1 13 SD/HD OUT2 12 SD/HD OUT3 11 NC (Top View) SD IN2 2 SD ...1m 10M 100M -1 dB @ 6.7 MHz -3 dB @ 8.1 MHz -53 dB @ 27 MHz 30 20 10 0 -10 -20 -30 -40 -50 -60 -1...
Description Six-Channel Video Driver with Triple SD & Triple Selectable SD/HD Filters

File Size 207.40K  /  13 Page

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    LTC1064-409 LTC1064-4CSW

Linear Technology
Part No. LTC1064-409 LTC1064-4CSW
OCR Text ... 40 20 0 0 2 4 6 8 10 12 14 16 18 20 22 FREQUENCY (kHz) 1064-4 G02 Passband Group Delay VS = 7.5V TA = 25C fC = 20kHz f CLK = 1mHz, 50:1 1m 0 2 4 6 8 10 12 14 16 18 20 22 FREQUENCY (kHz) 1064-4 G03 10644fb 3 ...
Description Analog Filter
Low Noise, 8th Order, Clock Sweepable Cauer Lowpass Filter

File Size 134.77K  /  12 Page

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    M12L32162A-5.5BG M12L32162A09 M12L32162A-5.5TG M12L32162A-6TG M12L32162A-6BG

Elite Semiconductor Memory Technology Inc.
Part No. M12L32162A-5.5BG M12L32162A09 M12L32162A-5.5TG M12L32162A-6TG M12L32162A-6BG
OCR Text ...6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ...1m x 16 1m x 16 DQi CLK ADD Column Decoder Latency & Burst Length LCKE Programming Registe...
Description 1m x 16Bit x 2Banks Synchronous DRAM

File Size 758.82K  /  29 Page

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    CY7C1566V1808 CY7C1566V18-400BZC CY7C1566V18-400BZI CY7C1566V18-400BZXC CY7C1566V18-400BZXI CY7C1568V18-400BZXC

Cypress Semiconductor, Corp.
Part No. CY7C1566V1808 CY7C1566V18-400BZC CY7C1566V18-400BZI CY7C1566V18-400BZXC CY7C1566V18-400BZXI CY7C1568V18-400BZXC
OCR Text ...18), 9-bit words (CY7C1577V18), 18-bit words (CY7C1568V18), or 36-bit words (CY7C1570V18) that burst sequentially into or out of the device....1m x 36 Array 1m x 36 Array LD K K DOFF 36 Output Logic Control CLK Gen. R/W Read ...
Description 4M X 18 DDR SRAM, 0.45 ns, PBGA165 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

File Size 419.60K  /  28 Page

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    CY7C1543V18 CY7C1543V18-300BZC CY7C1543V18-300BZI CY7C1543V18-300BZXC CY7C1543V18-300BZXI CY7C1543V18-333BZC CY7C1543V18

Cypress Semiconductor
Part No. CY7C1543V18 CY7C1543V18-300BZC CY7C1543V18-300BZI CY7C1543V18-300BZXC CY7C1543V18-300BZXI CY7C1543V18-333BZC CY7C1543V18-333BZI CY7C1543V18-333BZXC CY7C1543V18-333BZXI CY7C1543V18-375BZC CY7C1543V18-375BZI CY7C1543V18-375BZXC CY7C1543V18-375BZXI CY7C1541V18-375BZC CY7C1556V18-375BZC CY7C1545V18-375BZC CY7C1545V18-333BZI CY7C1545V18-300BZC CY7C1545V18-300BZI CY7C1545V18-300BZXC CY7C1545V18-333BZC CY7C1545V18-300BZXI CY7C1541V18-300BZI CY7C1541V18-333BZI CY7C1541V18-333BZXI CY7C1541V18-333BZXC
OCR Text ...V18 - 8M x 9 CY7C1543V18 - 4M x 18 CY7C1545V18 - 2M x 36 Separate independent read and write data ports Supports concurrent transactions...1m x 18 Array 1m x 18 Array 1m x 18 Array 1m x 18 Array K K CLK Gen. Control Logic ...
Description 72-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
72-Mbit QDR?II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

File Size 983.61K  /  28 Page

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