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Integrated Device Technology, Inc.
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| Part No. |
IDTCSPT857CPAI IDTCSPT857CPFI
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| OCR Text |
...p and tvsop, 40-pin vfqfpn, and 56- pin vfbga packages description: the cspt857c is a pll based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(clk, clk ) to 10 differential output pairs (y ... |
| Description |
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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| File Size |
140.09K /
15 Page |
 View
it Online |
Download Datasheet
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Integrated Device Technology, Inc.
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| Part No. |
IDTCSPT857DPF IDTCSPT857DPFI IDTCSPT857DPAGI
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| OCR Text |
...p and tvsop, 40-pin vfqfpn, and 56- pin vfbga packages description: the cspt857d is a pll based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(clk, clk ) to 10 differential output pairs (y ... |
| Description |
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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| File Size |
138.75K /
15 Page |
View
it Online |
Download Datasheet |
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IDT
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| Part No. |
IDTCSPT857C
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| OCR Text |
...SSOP and TVSOP, 40-pin MLF, and 56-pin VFBGA packages
The CSPT857C is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9])... |
| Description |
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
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| File Size |
135.63K /
15 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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