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White Electronic Designs
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| Part No. |
WEDPN4M64V
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| OCR Text |
...he type of burst (sequential or interleaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 speci? es the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all... |
| Description |
4M x 64 SDRAM
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| File Size |
344.58K /
12 Page |
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Silicon Integrated System
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| Part No. |
SIS5502 SIS5503
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| OCR Text |
...ller uses a direct-mapped, bank-interleaved/non-interleaved scheme, which can be configured as either in the write through or write back mode. both standard and burst srams are supported. table 1 shows the cache sizes that are supported by ... |
| Description |
(SIS5501 - SIS5503) PCI Local Data Buffer
(SIS5501 - SIS5503) PCI System I/O
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| File Size |
655.43K /
137 Page |
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OKI SEMICONDUCTOR CO., LTD.
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| Part No. |
MSM5716C50
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| OCR Text |
... high effective bandwidth using interleaved transactions. rdrams are general purpose high-performance memory devices suitable for use in a broad range of applications including pc and consumer main memory, graphics, video, and any other ap... |
| Description |
2M×8 Dynamic RAM(2M×8动态RAM) 200万8动态RAM米8动态内存）
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| File Size |
619.27K /
45 Page |
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Analog Devices, Inc.
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| Part No. |
AD9761
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| OCR Text |
...aneously updating each dac. the interleaved i and q input data stream is presented to the digital interface circuitry, which consists of i and q latches as well as some additional control logic. the data is de-interleaved back into its orig... |
| Description |
Dual 10-Bit TxDAC with 23 Interpolation Filters(内插滤波器的0位D/A转换
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| File Size |
286.07K /
24 Page |
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ST Microelectronics
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| Part No. |
STLC60135
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| OCR Text |
...nt dual latency paths: fast and interleaved atms phy layer: cell processing (cell deline- ation, cell insertion, hec) adsls overhead management reed solomon encode/decode trellis encode/decode (viterbi) dmt mapping/ demapping over 256 carri... |
| Description |
TOSCA ADSL DMT TRANSCEIVER
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| File Size |
277.23K /
25 Page |
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意法半导
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| Part No. |
STLC60135
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| OCR Text |
...nt dual latency paths: fast and interleaved atm's phy layer: cell processing (cell deline- ation, cell insertion, hec) adsl's overhead management reed solomon encode/decode trellis encode/decode (viterbi) dmt mapping/ demapping over 256 car... |
| Description |
TOSCA ADSL DMT TRANSCEIVER
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| File Size |
192.87K /
25 Page |
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it Online |
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