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CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY7C1418AV18-267BZC
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| Description |
36-Mbit DDR-II SRAM 2-Word Burst architecture; architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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| File Size |
917.70K /
27 Page |
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Renesas Electronics Corporation.
Renesas Electronics, Corp.
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| Part No. |
M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M38232G4-XXXFP M38232G4-XXXHP M38233G4-XXXFP M38233G4-XXXHP M38234G4-XXXFP M38234G4-XXXHP M38235G4-XXXFP M38230G6-XXXFP M38230G6-XXXHP M38231G6-XXXFP M38231G6-XXXHP M38232G6-XXXFP M38232G6-XXXHP M38233G6-XXXFP M38233G6-XXXHP M38234G6-XXXFP M38234G6-XXXHP M38235G6-XXXFP M38235G6-XXXHP M38236G6-XXXHP M38237G6-XXXFP M38237G6-XXXHP M38238G6-XXXFP M38230G7-XXXFP M38230G7-XXXHP M38231G7-XXXFP M38231G7-XXXHP M38232G7-XXXFP M38232G7-XXXHP M38233G7-XXXFP M38233G7-XXXHP M38234G7-XXXFP M38234G7-XXXHP M38235G7-XXXFP M38235G7-XXXHP M38236G7-XXXFP M38236G7-XXXHP M38237G7-XXXFP M38237G7-XXXHP M38238G7-XXXFP M38238G7-XXXHP M38239G7-XXXFP M38239G7-XXXHP M38230G8-XXXFP M38230G8-XXXHP M38231G8-XXXFP M38231G8-XXXHP M38232G8-XXXFP M38232G8-XXXHP M38233G8-XXXFP M38233G8-XXXHP M38234G8-XXXFP M38234G8-XXXHP M38235G8-XXXFP M38235G8-XXXHP M38236G8-XXXFP M38236G8-XXXHP M38237G8-XXXFP M38237G8-XXXHP M38238G8-XXXFP M38238G8-XXXHP M38230GA-XXXFP M38230GA-XXXHP M38231GA-XXXFP M38231GA-XXXHP M38232GA-XXXFP M38232GA-XXXHP M38233GA-XXXFP M38233GA-XXXHP M38234GA-XXXFP M38234GA-XXXHP M38235GA-XXXFP M38235GA-XXXHP M38236GA-XXXFP M38236GA-XXXHP M38237GA-XXXFP M38237GA-XXXHP
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| Description |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst architecture; architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst architecture; architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst architecture; architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst architecture; architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) architecture; architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst architecture; architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst architecture; architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst architecture; architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst architecture; architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst architecture (2.5 Cycle Read Latency); architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst architecture (2.0 Cycle Read Latency); architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst architecture; architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) architecture; architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst architecture; architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst architecture; architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst architecture; architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst architecture; architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst architecture; architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst architecture; architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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| File Size |
901.80K /
76 Page |
View
it Online |
Download Datasheet |
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HIROSE ELECTRIC Co., Ltd.
Pulse Engineering, Inc.
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| Part No. |
PE-69011 R0003 23Z87SM PE-68602 23Z104SM 23Z105SM
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| Description |
Common Mode Choke Catalog for Datacom & Power - Datacom section - (10/02)
Dual EconoReset with Pushbutton
Common Mode Choke Catalog for Datacom & Power - Datacom section - (10/02) 共模电感产品的数据通信
3.3 Volt MicroMonitor Chip 共模电感产品的数据通信
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| File Size |
495.40K /
12 Page |
View
it Online |
Download Datasheet |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1371D-100AXI CY7C1371D-100BGI CY7C1373D-100BZI CY7C1373D-133AXI CY7C1371D-100BZC CY7C1371D-100BZI CY7C1373D-100AXC CY7C1373D-100AXI CY7C1371D-100AXC CY7C1373D-133AXC CY7C1371D-133AXI CY7C1373D-100BZC CY7C1371D-133BGC CY7C1371D-133BGI CY7C1371D-133AXC CY7C1373D-100BGC CY7C1373D-133BGC CY7C1373D-133BGXI CY7C1373D-133BZXC CY7C1373D-133BZXI CY7C1373D-133BZI CY7C1373D-133BGXC CY7C1373D-133BZC CY7C1371D-133BGXC CY7C1371D-100BGXI ICY7C1373D-100BGXI CY7C1373D-100BZXC CY7C1371D-100BZXC CY7C1371D-100BGC ICY7C1373D-100BGI
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| Description |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM architecture 1M X 18 ZBT SRAM, 8.5 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM architecture 18兆位（为512k × 36/1M × 18）流体系结构，通过与NoBLTM的SRAM
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM architecture 1M X 18 ZBT SRAM, 8.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA119
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM architecture 1M X 18 ZBT SRAM, 6.5 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA119
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| File Size |
449.66K /
30 Page |
View
it Online |
Download Datasheet |
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