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IDT
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| Part No. |
IDT72V73250 72V73250_DS
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| OCR Text |
... useful in compensating for the skew between input streams. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5 master clock (C32i) periods... |
| Description |
TSI-TDM Switches
From old datasheet system
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| File Size |
165.91K /
24 Page |
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it Online |
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Analog Devices, Inc.
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| Part No. |
AD808
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| OCR Text |
... ) 80%C20% 136 315 500 ps clock skew (t rcs ) positive number indicates clock leading data C100 130 250 ps specifications subject to change without notice. (t a = t min to t max , v s = v min to v max , c d = 0.47 m f, unless otherwis... |
| Description |
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming(具有量化器和时钟恢复和数据再定时功能的光纤接收器)
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| File Size |
111.98K /
12 Page |
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it Online |
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Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
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| Part No. |
MAX3981
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| OCR Text |
...ge Transition Time Differential Skew Output Resistance tf, tr 20% to 80% (Notes 3, 4) Difference in 50% crossing between OUT_+ and OUT_- (No...compensating for frequency-dependent, mediainduced loss. The equalization control detects the spectr... |
| Description |
3.125Gbps XAUI Quad Cable Equalizer
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| File Size |
766.90K /
9 Page |
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it Online |
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IDT
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| Part No. |
IDT72V70210
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| OCR Text |
... useful in compensating for the skew between clocks. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +4 master clock (CLK) periods forward w... |
| Description |
TSI-TDM Switches
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| File Size |
110.43K /
19 Page |
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it Online |
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IDT
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| Part No. |
IDT72V73250BB IDT72V73250DA
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| OCR Text |
... useful in compensating for the skew between input streams. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5 master clock (C32i) periods... |
| Description |
8K x 8K TSI, 16 I/O at 32Mbps, 3.3V
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| File Size |
168.26K /
24 Page |
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it Online |
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IDT
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| Part No. |
IDT72V73260BB IDT72V73260DA
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| OCR Text |
... useful in compensating for the skew between input streams. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5 master clock (C32i) periods... |
| Description |
16K x 16K TSI, 32 I/O at 32Mbps, 3.3V
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| File Size |
191.35K /
26 Page |
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it Online |
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Analog Devices, Inc.
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| Part No. |
AD808 AD808-622BR AD808-622BRRL AD808-622BRRL7 AD60007
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| OCR Text |
... ) 80%C20% 136 315 500 ps clock skew (t rcs ) positive number indicates clock leading data C100 130 250 ps specifications subject to change without notice. (t a = t min to t max , v s = v min to v max , c d = 0.47 m f, unless otherwis... |
| Description |
622 Mbps, Low Power, Post-Amp/Clock and Data Recovery IC
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming RECEIVER, PDSO16
Ic = 500 mA; Package: PG-SOT223-4; Polarity: NPN; VCEO (max): 60.0 V; Ptot (max): 2,000.0 mW; hFE (min): 100.0 - 250.0; IC: 1,000.0 mA;
16-Bit, 250ksps, Single Supply ADC; Package: SSOP; No of Pins: 28; Temperature Range: -40°C to 85°C
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| File Size |
147.56K /
12 Page |
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it Online |
Download Datasheet |
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For
skew-compensating Found Datasheets File :: 34 Search Time::1.172ms
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