Description |
lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture 1M lor='#FF0000'>x 1lor='#FF0000'>8 ZBT SRAM, 3 ns, PQFP100 lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture 1M lor='#FF0000'>x 1lor='#FF0000'>8 ZBT SRAM, 3 ns, PBGA165 lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture 1M lor='#FF0000'>x 1lor='#FF0000'>8 ZBT SRAM, 3 ns, PBGA119 lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture 1M lor='#FF0000'>x 1lor='#FF0000'>8 ZBT SRAM, 2.lor='#FF0000'>8 ns, PBGA119 lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture 1M lor='#FF0000'>x 1lor='#FF0000'>8 ZBT SRAM, 2.lor='#FF0000'>8 ns, PBGA165 lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture lor='#FF0000'>512k lor='#FF0000'>x 36 ZBT SRAM, 3 ns, PBGA165 lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture lor='#FF0000'>512k lor='#FF0000'>x 36 ZBT SRAM, 3 ns, PQFP100 lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture lor='#FF0000'>512k lor='#FF0000'>x 36 ZBT SRAM, 3.4 ns, PQFP100 lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture lor='#FF0000'>512k lor='#FF0000'>x 36 ZBT SRAM, 3.4 ns, PBGA165 lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBlArchitecture 12k × 36/1M × 1lor='#FF0000'>8流水线的SRAM架构的总线延迟 CAP,Ceramic,10000pF,500VDC,10-% Tol,10% Tol,lor='#FF0000'>x7R-TC Code,-15,15%-TC,30ppm-TC RoHS Compliant: Yes lor='#FF0000'>512k lor='#FF0000'>x 36/1M lor='#FF0000'>x 1lor='#FF0000'>8 Pipelined SRAM with NoBl Architecture
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