|
|
|
Samsung Electronic
|
Part No. |
M368L0914DT2
|
OCR Text |
...arge; trc=trcmin;tck=100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle idd0 - - operating current - one bank operation ; one bank ... |
Description |
8Mx64 DDR SDRAM 184pin DIMM based on 8Mx16 Data Sheet
|
File Size |
93.17K /
16 Page |
View
it Online |
Download Datasheet |
|
|
|
HYNIX SEMICONDUCTOR INC
|
Part No. |
HY5DU56422DF-H HY5DU56422DF-K
|
OCR Text |
...v dd , v ddq = 2.5v 0.2v for ddr200, 266, 333 v dd , v ddq = 2.6v 0.1v for ddr400 ? all inputs and outputs ar e compatible with sstl_2 interface ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? so... |
Description |
64M X 4 DDR DRAM, 0.75 ns, PBGA60
|
File Size |
268.38K /
31 Page |
View
it Online |
Download Datasheet |
|
|
|
Samsung Electronic
|
Part No. |
M368L3223CTL
|
OCR Text |
...e(tis/tih) at slow slew rate in ddr200/266 ac specification 5. deleted exit self refresh to write command(txsw) in ddr200/266 ac specification 6. changed unit of tmrd from tck to ns at ddr333 7. rename txsa(exit self refresh to bank active ... |
Description |
32Mx64 DDR SDRAM 184pin DIMM based on 32Mx8 Data Sheet
|
File Size |
94.43K /
16 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|