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				Vishay Intertechnology, Inc. TOKO, Inc. BI Technologies, Corp. Thomas Aavid Thermalloy, LLC
Part No.	CLA76000ACP208 CLA76000GC172 CLA76000GCP132 CLA76000GCP196 CLA76000GG160 CLA75000AC132 CLA76000AC180 CLA76000GC196 CLA76000GP160 CLA76000GCP172 CLA76000ACP144 CLA75000AC144 CLA77000ACP144 CLA78000ACP144 CLA77000GCP256 CLA78000GCP256 CLA72000HG68 CLA72000GG64 CLA73000HG68 CLA71000HG68 CLA71000GG64 CLA73000GG64 CLA70000MP16L CLA71000GG52 CLA70000MC24 CLA70000DP40 CLA78000AC257 CLA70000HG44 CLA73000GG100 CLA73000GG120 CLA73000GP80 CLA73000LC84 CLA74000GG80 CLA74000GP80 CLA74000GG100 CLA74000GG120 CLA73000GP120 CLA73000HC84 CLA77000AC180
OCR Text	...ependent on circuit structure, giving a range of 40 -70% for two layer metallisation. cla70000 series high density cmos gate arrays march 1992 recent advances in cmos processing technology and improvements in design architecture have led t...
Description	ASIC 专用集成电路
File Size	245.07K / 17 Page	View it Online	Download Datasheet

				Mitel Semiconductor Mitel Networks Corporation
Part No.	SL2017 SL2017KG SL2017MP1S SL2017MP1T
OCR Text	... divider to a divide by 16 mode giving a 250khz phase comparator frequency with a 500khz step size when a 4mhz crystal is used. 40 is charge pump and port control data (byte 5). the code 40 will set the charge pump current to 260ua. all por...
Description	4.75-5.25V; full base satellite tuner. For satellite tuners, commnucations systems Full Band Satellite Tuner(应用在卫星调谐器方面的完全集成混频器)
File Size	194.82K / 17 Page	View it Online	Download Datasheet

				PhaseLink, Corp. PhaseLink Corporation
Part No.	PL611S-02-XXXTIR PL611S-02-XXXUC-R PL611S-02-XXXUCR PL611S-02-XXXUIR PL611S-02-XXXGC-R PHASELINKCORPORATION-PL611S-02-XXXGIR
OCR Text	...orates a 60kn pull up resistor giving a default condition of logic 1. power-down control (pdb) the power down (pdb) feature allows the user to put the pl611s-02 into sleep mode. when activated (logic 0), pdb disables the pll, the osc...
Description	1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock 1.8 - 3.3VPicoPLLTM，世界上最小的可编程时 1.8V-3.3V PicoPLLTM, Worlds Smallest Programmable Clock 1.8 - 3.3V的PicoPLLTM，世界上最小的可编程时 1.8V-3.3V PicoPLLTM, World?? Smallest Programmable Clock
File Size	214.81K / 8 Page	View it Online	Download Datasheet

				PhaseLink, Corp.
Part No.	PL611S-28-XXXTI PL611S-28-XXXTC PL611S-28-XXXTC-R
OCR Text	...orates a 60kk pull up resistor giving a default condition of logic 1. the oe feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. power-down control (pdb) the power down (pdb) feature...
Description	1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock 1.8 - 3.3VPicoPLLTM，世界上最小的可编程时 1.8V-3.3V PicoPLLTM, Worlds Smallest Programmable Clock 1.8 - 3.3V的PicoPLLTM，世界上最小的可编程时
File Size	324.53K / 9 Page	View it Online	Download Datasheet

				PhaseLink, Corp.
Part No.	PL611S-18-XXXTI PL611S-18-XXXTIR PL611S-18-XXXUI PL611S-18-XXXTC-R PL611S-18-XXXGC-R PHASELINKCORPORATION-PL611S-18-XXXUIR
OCR Text	...rates a 60kn pull up resist or giving a default condition of logic 1. pulling t he oe pin low 0 will tri-state the output buffers. power-down control (pdb) the power down (pdb) feature allows the user to put the pl611s-18 into sleep...
Description	0.5kHz-125MHz MHz to KHz Programmable ClockTM 0.5kHz - 125MHz的频率，以千赫的可编程ClockTM
File Size	223.70K / 9 Page	View it Online	Download Datasheet

				PhaseLink, Corp.
Part No.	PL611S-17-XXXGCR PL611S-17-XXXTCR PL611S-17-XXXTI PL611S-17-XXXGI PL611S-17-XXXTIR PL611S-17-XXXUIR
OCR Text	...rates a 10mn pull up resist or giving a default condition of logic 1. the oe feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. power-down control (pdb) the power down (pdb) feature...
Description	1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock 1.8 - 3.3V的PicoPLLTM千赫到MHz可编程时
File Size	222.89K / 9 Page	View it Online	Download Datasheet

				PhaseLink, Corp.
Part No.	PL611S-19-XXXUCR PL611S-19-XXXTC-R PL611S-19-XXXGCR PL611S-19-XXXUC-R PL611S-19-XXXUIR PL611S-19-XXXGC-R PL611S-19-XXXGIR
OCR Text	...orates a 60ko pull up resistor giving a default condition of logic 1. the oe feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. power-down control (pdb) the power down (pdb) feature...
Description	0.5kHz-55MHz MHz to KHz Programmable ClockTM 0.5kHz - 55MHz的兆赫至千赫的可编程ClockTM
File Size	207.59K / 8 Page	View it Online	Download Datasheet

				PhaseLink, Corp.
Part No.	PL611S-26-XXXGIR PL611S-26-XXXGC PL611S-26-XXXTC-R PL611S-26-XXXTI
OCR Text	...orates a 60kl pull up resistor giving a default condition of logic 1 . output enable (oe) the output enable feature allows the user to enable and disable the clock output(s) by toggling the oe pin. the oe pin incorporates a 60kl pull...
Description	1.8V-3.3V PicoPLLTM Programmable Clock 1.8 - 3.3V的可编程时钟PicoPLLTM
File Size	199.01K / 8 Page	View it Online	Download Datasheet

				Avago Technologies, Ltd. PhaseLink, Corp.
Part No.	PL611S-27-XXXGC PL611S-27-XXXGC-R
OCR Text	...orates a 60ko pull up resistor giving a default condition of logic 1. the oe feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. power-down control (pdb) the power down (pdb) feature...
Description	1.8V to 3.3V PicoPLLTM Programmable Clock 1.8V.3V PicoPLLTM可编程时
File Size	213.34K / 9 Page	View it Online	Download Datasheet

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