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  lvpecl hstl Datasheet PDF File

For lvpecl hstl Found Datasheets File :: 485    Search Time::1.391ms    
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    MAXIM[Maxim Integrated Products]
MAXIM - Dallas Semiconductor
Part No. MAX9375 MAX9375EUA
OCR Text lvpecl Translator General Description The MAX9375 is a fully differential, high-speed, anything-to-lvpecl translator designed for signal r...hstl, and CML differential signaling standards. Outputs are lvpecl and have sufficient current to dr...
Description Single LVDS/Anything-to-lvpecl Translator

File Size 131.88K  /  6 Page

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    Fairchild
Part No. FIN1101
OCR Text ...uencies. It can directly accept lvpecl, hstl, and SSTL-2 for translating directly to LVDS. Features s Greater than 800 Mbps full differential path s 3.5 ps max random jitter and 135 ps max deterministic jitter s 3.3V power supply operat...
Description LVDS Single Port High Speed Repeater

File Size 251.13K  /  6 Page

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    Freescale (Motorola)
FREESCALE[Freescale Semiconductor, Inc]
Freescale Semiconductors
飞思卡尔半导体(中国)有限公司
Part No. MC100ES6039 MC100ES6039EGR2 MC100ES6039DW MC100ES6039DWR2 MC100ES6039EG
OCR Text ...sitive power supplies are used, lvpecl input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the d...hstl Input Compatible 20-Lead Pb-Free Package Available MC100ES6039 DW SUFFIX 20-LEAD SOIC PAC...
Description 3.3 V ECL/PECL/hstl/LVDS /-2/4, /-4/5/6 Clock Generation Chip
3.3V ECL/PECL/hstl/LVDS 2/4, 4/6 Clock Generation Chip 3.3 ECL / PECL hstl / LVDS / 44 / 6时钟发生器芯

File Size 228.41K  /  8 Page

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    Motorola
Part No. MC100ES6221
OCR Text ...tandards. CLK0 is compatible to lvpecl signals and CLK1 meets both hstl differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage (VCMR). VPP (DC) is the minimum differential input ...
Description Low Voltage 1:20 Dlfferentlal ECL/PECL hstl Clock Fanout Buffer

File Size 111.77K  /  12 Page

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    Integrated Circuit Syst...
ICST[Integrated Circuit Systems]
Part No. ICS852911I ICS852911AVI ICS852911AVIT
OCR Text ...table differential CLK, nCLK or lvpecl clock inputs * hstl_CLK, nhstl_CLK pair can accept the following differential input levels: lvpecl, LVDS, hstl, SSTL, HCSL * PECL_CLK, nPECL_CLK supports the following input types: lvpecl, CML, SSTL * ...
Description Low Skew, 1-to-9, Differential-to-hstl Fanout Buffer. VOHmax=1.4V. Industrial Temperature.
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-hstl FANOUT BUFFER

File Size 202.81K  /  15 Page

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    Xilinx
Part No. XC2S300E-6PQ208C
OCR Text ... SSTL, AGP, CTT, GTL * LVDS and lvpecl differential I/O - Up to 205 differential I/O pairs that can be input, output, or bidirectional - Hot swap I/O (CompactPCI friendly) Fully supported by powerful Xilinx ISE development system - Fully au...
Description IC,FPGA,6912-CELL,CMOS,QFP,208PIN,PLASTIC

File Size 41.78K  /  4 Page

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    Xilinx
Part No. XC3S5000 XC3S400 XC3S4000 XC3S2000
OCR Text ... N/A Standard Bus Extended Mode lvpecl RSDS hstl SSTL Low-Voltage Positive Emitter-Coupled Logic Reduced-Swing Differential Signaling Differential High-Speed Transceiver Logic Differential Stub Series Terminated Logic 2.5 2.5 1.8 2.5 N/A N/...
Description (XC3S50 - XC3S5000) Spartan-3 FPGA Family

File Size 1,763.79K  /  204 Page

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