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Agilent (Hewlett-Packard)
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Part No. |
1691A 1693AD 1680A 1680AD
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OCR Text |
... State clock/qualifiers Minimum master-to-master clock time Minimum master-to-slave clock time Minimum slave-to-master clock time Setup/hold...target system
Agilent provides probing solutions that deliver a solid electrical and mechanical con... |
Description |
1690A PC-Hosted Logic Analyzer with 800 MHz Timing/200 MHz State 136 Channels 1M Memory 1693AD PC-Hosted Logic Analyzer with 800 MHz Timing/200 MHz State 34 Channels 4M Memory 1690AD PC-Hosted Logic Analyzer with 800 MHz Timing/200 MHz State 136 Channels 4M Memory 1680AD Standalone Logic Analyzer with 800 MHz Timing/200 MHz State 136 Channels 4M Memory
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File Size |
1,214.80K /
13 Page |
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it Online |
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QUICKLOGIC CORP
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Part No. |
QL902M200-2PSN544C
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OCR Text |
...ons support for external bus master arbitration (through fpga library provided by quicklogic) two ethernet controllers two 10/100 ma...target ! pci target access to system address space ! pci target to pci configuration registers ! pci... |
Description |
FPGA, 2016 CLBS, 533000 GATES, PBGA544
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File Size |
703.84K /
106 Page |
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it Online |
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Agilent (Hewlett-Packard)
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Part No. |
1672G
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OCR Text |
...ount between states [3] Minimum master-to-master clock time* Minimum master-to-slave clock time Minimum slave-to-master clock time Clock qualifier setup/hold 3.5 ns 8 ns or 0.1% (whichever is greater) 34.4 seconds 4.29 x 109 states 6.67 ns... |
Description |
1672G Standalone Logic Analyzer with 500 MHz Timing/150 MHz State 68 Channels 128K Memory
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File Size |
1,657.90K /
24 Page |
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it Online |
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MosChip Semiconductor
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Part No. |
MCS9845
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OCR Text |
... is asserted by the current Bus master to indicate the beginning of an transfer. nFRAME remains active until the last Byte of the transfer i...target device. target Ready (three-state). Asserted when the target is ready to complete the current... |
Description |
PCI Dual UART
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File Size |
480.60K /
28 Page |
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it Online |
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PLX Technology, Inc.
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Part No. |
PEX8111-BB66FBC PEX8111-BB66BC PEX8111-BB66FBCF PEX8111-BB66BCF
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OCR Text |
...at returns a completion to the master. ns no snoop. o cmos output. od open drain output. originating bus master of a transacti on that cros...target. pci target claims the transaction by asserting devsel# and handshakes the transaction (trdy... |
Description |
ExpressLanePCI Express to PCI Bridge PCI BUS CONTROLLER, PBGA161 ExpressLanePCI Express to PCI Bridge PCI BUS CONTROLLER, PBGA144
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File Size |
2,223.00K /
286 Page |
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it Online |
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DALLAS[Dallas Semiconducotr] DALLAS[Dallas Semiconductor] MAXIM - Dallas Semiconductor Linear Technology, Corp.
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Part No. |
DS1993L-F5 DS1994L-F5 DS1992 DS1992L-F5
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OCR Text |
...conomically Communicates to Bus master with a Single Digital Signal at 16.3kbps Standard 16mm Diameter and 1-Wire(R) Protocol Ensure Compati...target address (TA1, TA2). The third register is the ending offset/data status byte (E/S). The targe... |
Description |
1kbit/4kbit Memory iButtonTM DS1994 4-kbit Plus Time Memory iButtonTM 1kbit/4kbit Memory iButtonTM DS1994 4-kbit Plus Time Memory iButtonTM 1kbit/4kbit内存iButtonTM DS1994 4千位加时间内存iButtonTM
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File Size |
220.64K /
17 Page |
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it Online |
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Price and Availability
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