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| Part No. |
CY25245
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| OCR Text |
.... the input reference signal is divided by q and fed to the phase detector. a signal from the vco is divided by p and fed back to the phase detector also. the pll will force the frequency of the vco output signal to change until the divided... |
| Description |
Clocks and Buffers
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| File Size |
117.89K /
11 Page |
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it Online |
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CYPRESS[Cypress Semiconductor]
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| Part No. |
W183 W183-5 W183G W183-5G
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| OCR Text |
.... The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided... |
| Description |
Clocks and Buffers : Application Specific Clocks
Full Feature Peak Reducing EMI Solution
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| File Size |
124.04K /
9 Page |
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it Online |
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Zarlink
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| Part No. |
MT8940 118
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| OCR Text |
... in Figure 3. A master clock is divided down to 8 kHz where it is compared with the 8 kHz input, and depending on the output of the phase comparison, the master clock frequency is corrected. The MT8940 achieves the frequency correction in b... |
| Description |
ISO-CMOS ST-BUS? FAMILY
From old datasheet system
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| File Size |
492.69K /
19 Page |
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it Online |
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LAPIS SEMICONDUCTOR CO LTD
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| Part No. |
MSM5265GS-BK MSM5265GS-K
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| OCR Text |
...al is formed. this frequency is divided into either 1/8 or 1/4 by the internal dividing circuit. the 1/8 divided frequency is used in the static display mode, while the 1/4 divided frequency is used as the common signal in the 1/2 duty dyna... |
| Description |
LIQUID CRYSTAL DISPLAY DRIVER, PQFP100
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| File Size |
179.79K /
19 Page |
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it Online |
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Price and Availability
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