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MOTOROLA[Motorola, Inc]
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| Part No. |
MPC9658
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| OCR Text |
...MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9658... |
| Description |
3.3V 1:10 LVCMOS PLL Clock Generator
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| File Size |
290.07K /
12 Page |
 View
it Online |
Download Datasheet
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MOTOROLA[Motorola, Inc]
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| Part No. |
MPC9653
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| OCR Text |
...MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653... |
| Description |
3.3V 1:8 LVCMOS PLL CLOCK GENERATOR
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| File Size |
290.68K /
12 Page |
View
it Online |
Download Datasheet |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
5V19EE903PGGI
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| OCR Text |
...are a total of six 8-bit output dividers. the outputs are connected to the plls via a switch matrix. the switch matrix allows the user to route the pll outputs to any output bank. this feature can be used to simplify and optimize the bo... |
| Description |
5V SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
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| File Size |
280.32K /
31 Page |
View
it Online |
Download Datasheet |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
5V19EE404NLGI
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| OCR Text |
...re a total of four 8-bit output dividers.the outputs are connected to the plls via a switch matrix. the switch matrix allows the user to route the pll outputs to any output bank. this feature can be used to simplify and optimize the boa... |
| Description |
5V SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC24
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| File Size |
262.71K /
29 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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