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ICS
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| Part No. |
ICS9248-50
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| OCR Text |
...P# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-50. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
PC... |
| Description |
CK100 Main Clock for BX Mobile, Supports 66.6 - 100MHz
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| File Size |
239.65K /
10 Page |
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it Online |
Download Datasheet
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Integrated Device Technology, Inc.
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| Part No. |
9248YG-92GLFT
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| OCR Text |
...p# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9248-92. 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state.
idt... |
| Description |
PROC SPECIFIC CLOCK GENERATOR, PDSO48 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
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| File Size |
557.37K /
16 Page |
View
it Online |
Download Datasheet |
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NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
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| Part No. |
74F50728 N74F50728N I74F50728D I74F50728N N74F50728D
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| OCR Text |
...op
74F50728
FEATURES
* metastable immune characteristics * Output skew less than 1.5ns * See 74F5074 for synchronizing dual D-type flip-flop * See 74F50109 for synchronizing dual J-K positive edge-triggered
flip-flop
Clock trig... |
| Description |
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
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| File Size |
93.13K /
12 Page |
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it Online |
Download Datasheet |
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Price and Availability
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