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For pll-based Found Datasheets File :: 9395    Search Time::3.031ms    
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    HDMP-1022 HDMP-1024

Agilent (Hewlett-Packard)
HP[Agilent(Hewlett-Packard)]
Part No. HDMP-1022 HDMP-1024
OCR Text ...CONTROL LOGIC + C-FIELD ENCODER PLL / CLOCK GENERATOR MDFSEL M20SEL STRBIN DIV0 DIV1 RFD CAP0 0.1 F CAP1 ED LATCH ...based on a supplied frame clock (STRBIN) and control signals (M20SEL, MDFSEL, EHCLKSEL, DIV1, DIV0)....
Description Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

File Size 292.53K  /  40 Page

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    HDMP-1512 HDMP-1514

Agilent (Hewlett-Packard)
HP[Agilent(Hewlett-Packard)]
Part No. HDMP-1512 HDMP-1514
OCR Text ...2 LOUT 2 SO 2 TBC PLL/CLOCK GENERATOR INTERNAL CLOCKS LASER DRIVER LZOUT LASER CONTROLS -LZON PPSEL Figure 2. HDM...based on the selected baud rate. The baud rate is controlled by the appropriate setting of the SPDSE...
Description Fibre Channel Transmitter and Receiver Chipset

File Size 245.24K  /  26 Page

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    HDMP-1526

HP[Agilent(Hewlett-Packard)]
Agilent (Hewlett-Packard)
Part No. HDMP-1526
OCR Text ...ock). The transmitter section's PLL locks to this user supplied 106.25 MHz byte clock. This clock is multiplied by 10, to generate the 1062....based on the supplied reference byte clock (REFCLK). REFCLK is used as both the frequency reference ...
Description Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit
Fibre Channel Transceiver Chip

File Size 217.05K  /  14 Page

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    HDMP-1536 HDMP-1546

Agilent (Hewlett-Packard)
HP[Agilent(Hewlett-Packard)]
Part No. HDMP-1536 HDMP-1546
OCR Text ...ock). The transmitter section's PLL locks to this user supplied 106.25 MHz byte clock. This clock is then multiplied by 10, to generate the ...based on the supplied reference byte clock (REFCLK). REFCLK is used as both the frequency reference ...
Description Fibre Channel Transceiver Chip

File Size 246.58K  /  15 Page

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    HDMP-1636 HDMP-1646

Dantona Industries, Inc.
HP[Agilent(Hewlett-Packard)]
Agilent (Hewlett-Packard)
Part No. HDMP-1636 HDMP-1646
OCR Text ...ock). The transmitter section's PLL locks to this user supplied 125 MHz byte clock. This clock is then multiplied by 10, to generate the 125...based on the supplied reference byte clock (REFCLK). REFCLK is used as both the frequency reference ...
Description Gigabit Ethernet Transceiver Chip 千兆以太网收发器芯片
Software

File Size 314.09K  /  15 Page

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    PCK953BD PCK953

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. PCK953BD PCK953
OCR Text PLL clock driver Product specification Supersedes data of 2000 Oct 25 ICL03 -- PC Motherboard ICs; Logic Products Group 2001 Feb 08 Phil...based clock driver device targeted for high performance clock tree designs. With output frequencies ...
Description 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

File Size 65.55K  /  8 Page

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    ICS843004 ICS843004AG ICS843004AGT

ICST[Integrated Circuit Systems]
Part No. ICS843004 ICS843004AG ICS843004AGT
OCR Text ...ace levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Pul...
Description FEMTOCLOCKS LVCMOS/CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
FEMTOCLOCKS⑩ LVCMOS/CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER

File Size 288.06K  /  16 Page

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    ICS9176-01 ICS9176M-01 AV9176M-01 ICS9176Q-01

ICST[Integrated Circuit Systems]
Part No. ICS9176-01 ICS9176M-01 AV9176M-01 ICS9176Q-01
OCR Text ...The internal phase locked loop (PLL) acts either as a 1X clock multiplier or a 1/2X clock multiplier depending on the state of the input con...based 1086E. The typical operating current for the ICS9176-01 is 60mA versus 115mA for the GA1086E. ...
Description Low Skew Output Buffer

File Size 377.43K  /  8 Page

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    ICS9177 ICS9177-01CF52

ICST[Integrated Circuit Systems]
Part No. ICS9177 ICS9177-01CF52
OCR Text ...om external oscillator external PLL Feedback path from one of the OutC outputs PLL divider mode control (Contains internal pull-up resistors) Test mode ENABLE pin External Test Clk TTL - 25 MHz output clock TTL - 12.5 MHz output clock ...
Description High Frequency System Clock Generator

File Size 314.80K  /  8 Page

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