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IDT
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Part No. |
ICSSSTUAF32866B
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OCR Text |
...he second register produces to ppo and qerr signals. the qerr of the first register is left floating. the valid error information is latched on the qerr output of the second register. if an error occurs qerr is latched low for two ... |
Description |
25-BIT CONFIGURABLE REGISTERED BUFFER
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File Size |
581.73K /
31 Page |
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it Online |
Download Datasheet
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ICS
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Part No. |
ICSSSTUA32S869B
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OCR Text |
...trols and will force the qn and ppo outputs low and the ptyerr1# high. the icssstua32s869b includes a parity checking function. the icssstua32s869b accepts a parity bit from the memory controller at its input pin parin1 one or two cycle... |
Description |
14-Bit Configurable Registered Buffer
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File Size |
319.50K /
18 Page |
View
it Online |
Download Datasheet
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