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Fairchild
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| Part No. |
DM74LS373 DM74LS374
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| OCR Text |
...f the DM74LS373 are transparent dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eig... |
| Description |
3-STATE Octal D-Type Transparent Latches
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| File Size |
82.92K /
8 Page |
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it Online |
Download Datasheet
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Fairchild
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| Part No. |
CD40175BC CD40174BC
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| OCR Text |
... of six positive-edge triggered dtype flip-flops; the true outputs from each flip-flop are externally available. The CD40175BC consists of four positiveedge triggered D-type flip-flops; both the true and complement outputs from each flip-fl... |
| Description |
Hex D-Type Flip-Flop • Quad D-Type Flip-Flop
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| File Size |
67.32K /
7 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT74ALVCH32501
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| OCR Text |
...501 combines D-type latches and dtype flip-flops to allow data flow in transparent latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLK... |
| Description |
3.3V CMOS 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
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| File Size |
147.86K /
8 Page |
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it Online |
Download Datasheet |
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SGS Thomson Microelectronics
ST Microelectronics
STMICROELECTRONICS[STMicroelectronics]
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| Part No. |
M74HCT174 M54HCT174 2111 M74HCT174B1R M74HCT174M1R M54HCT174F1R M74HCT174C1R
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| OCR Text |
...HCT174 is a high speed CMOS HEX dtype FLIP-FLOP WITH CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Information signals applied to D inputs a... |
| Description |
HEX D-TYPE FLIP FLOP WITH CLEAR
From old datasheet system
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| File Size |
243.99K /
11 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT74LVC16501A
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| OCR Text |
...stered bus transceiver combines dtype latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by outputenable (OEAB and OEBA), latch enable (LEAB and LEBA) and c... |
| Description |
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
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| File Size |
68.47K /
6 Page |
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it Online |
Download Datasheet |
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Price and Availability
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