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pll-ii Datasheet PDF File

For pll-ii Found Datasheets File :: 2685 Search Time::1.281ms
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				Microsemi Corporation
Part No.	FG324 IO96PDB2V1 IO99NDB2V2 IO99PDB2V2 IO83PSB2V0 A3P3000L VQ100
OCR Text	... conditioning circuit (ccc) and pll ? six ccc blocks, one with integrated pll (proasic3l) and all with integrated pll (proasic3el) ? config...ii revision 13 i/os per package 1 proasic3l low-power devices a3p250l 2 a3p600l a3p1000l a3pe3000l a...
Description	ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology
File Size	11,714.05K / 242 Page	View it Online	Download Datasheet

				IDT[Integrated Device Technology]
Part No.	IDT5V9950 IDT5V9950PFI
OCR Text	PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCKTM II JR. FEATURES: * * * * * * * * * * * * * * Ref input is 5V tolerant 4 pairs of programmable skew outputs Low skew...
Description	3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK? II JR.
File Size	65.38K / 9 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1263XV18 CY7C1265XV18-633BZXC CY7C1263XV18-600BZXC
OCR Text	...access port phase-locked loop (pll) for accurate data placement configurations with read cycle latency of 2.5 cycles: cy7c1263xv18 ? 2 m 1...ii+ architecture. similar to qdr ii architecture, qdr ii+ architecture consists of two separate port...
Description	36-Mbit QDR? II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDRII Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
File Size	1,180.83K / 30 Page	View it Online	Download Datasheet

				Altera Corporation
Part No.	EP2SGX60C EP2SGX30CF780C5N EP2SGX30D EP2SGX60CF780C4N EP2SGX130G
OCR Text	...h, clock switch-over, real-time pll reconfiguration, and advanced multiplication and phase shifting support for numerous single-ended and...ii gx device handbook, volume 1 october 2007 features support for multiple intellectual property m...
Description	Section I. Stratix II GX Device Data Sheet Support for numerous single-ended and differential I/O standards Section I. Stratix II GX Device Data Sheet
File Size	1,800.82K / 316 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1425KV18
OCR Text	...access port phase locked loop (pll) for accurate data placement configurations cy7c1425kv18 ? 4 m 9 cy7c1412kv18 ? 2 m 18 cy7c1414kv18 ? ...ii architecture. qdr ii architecture consists of two separate ports: the read port and the write po...
Description	36-Mbit QDR? II SRAM Two-Word Burst Architecture
File Size	618.73K / 33 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1645KV18 CY7C1643KV18-450BZI CY7C1643KV18-400BZC CY7C1645KV18-400BZXI
OCR Text	...access port phase locked loop (pll) for accurate data placement configurations with read cycle latency of 2.0 cycles: cy7c1643kv18 ? 8 m ...ii+ architecture. similar to qdr ii architecture, qdr ii+ architecture consists of two separate port...
Description	144-Mbit QDR? II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
File Size	613.62K / 31 Page	View it Online	Download Datasheet

				Cypress Semiconductor Corp.
Part No.	CYP15G0403DXB-BGXI CYP15G0403DXB-BGXC CYV15G0403DXB-BGXI CYV15G0403DXB-BGC CYV15G0403DXB-BGI CYV15G0403DXB-BGXC CYP15G0403DXB-BGI CYW15G0403DXB-BGXI
OCR Text	...d loops (plls) with no external pll components ? dual differential pecl-compatible serial inputs per channel ? internal dc-restoration ? du...ii? transceiver is a poi nt-to-point or point-to-multi- point communications building block enabling...
Description	Independent Clock Quad HOTLink IITransceiver Independent Clock Quad HOTLink II??Transceiver
File Size	515.97K / 45 Page	View it Online	Download Datasheet

				Altera
Part No.	EP2S30XXX EP2S15XXX EP2S130XXX EP2S90XXX EP2S180XXX EP2S60F672C3
OCR Text	...dated introduction text in the "PLL Timing Specifications" section. Re-organized chapter. Added typical values and CO U T F B to Table 5-30....II Device Handbook. 6 January 2005, v2.0 October 2004, v1.1 Contact information was removed. Updated...
Description	(EP2Sxxx) Stratix II Device Family
File Size	1,036.32K / 204 Page	View it Online	Download Datasheet

				Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
Part No.	CYV15G0104TRB-BGXC
OCR Text	...d loops (plls) with no external pll components ? supports half-rate and full-rate clocking ? selectable differential pecl-compatible serial...ii? serializer and reclocking deserializer is a point-to-point or point-to-multipoint communications...
Description	Independent Clock HOTLink IISerializer and Reclocking Deserializer SPECIALTY TELECOM CIRCUIT, PBGA256
File Size	365.64K / 28 Page	View it Online	Download Datasheet

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