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Xilinx
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| Part No. |
XC2S200E
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| OCR Text |
... alternative to mask-programmed asics. the fpga avoids the initial cost, lengthy development cycles, and inherent risk of conventional asics. also, fpga programmability permits design upgrades in the field with no hardware replacement neces... |
| Description |
(XC2SxxxE) Spartan IIE 1.8V FPGA Family
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| File Size |
836.47K /
103 Page |
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Integrated Silicon Solution Inc
Integrated Silicon Solution, Inc.
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| Part No. |
IS82C600 IS82C600-9BI IS82C600-8B
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| OCR Text |
...the re-use of already available asics and glue logic. a key benefit of the trailblazer device is its ability to relieve high-performance processors from a necessity to drive heavily loaded multidrop buses by providing a point-to- ? features... |
| Description |
Trailblazer High-speed SRAM with address decoding and ready logic
64K x 16 High-Speed SRAM with Address Decoding and Ready Logic(带地址译码器和预备逻辑的高速静态RAM)
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| File Size |
133.63K /
21 Page |
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Xilinx, Inc.
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| Part No. |
XC3S1000-4CP132C XC3S1000-4TQ144I XC3S1000-4PQ208C XC3S1000-4CP132I XC3S1000-4VQ100C XC3S1000-4PQ208I XC3S1000-4TQ144C XC3S1000-4VQG100C XC3S1000-4VQ100I XC3S1000-4VQG100I XC3S1000-5CP132C XC3S1000-4CPG132C XC3S1000-4TQG144I
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| OCR Text |
...lternative to mask pro- grammed asics. fpgas avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional asics. also, fpga programmability permits design upgrades in the field with no hardware... |
| Description |
Spartan-3 FPGA Family: Complete Data Sheet FPGA, 192 CLBS, 50000 GATES, PBGA132
Spartan-3 FPGA Family: Complete Data Sheet FPGA, 192 CLBS, 50000 GATES, PQFP100
Spartan-3 FPGA Family: Complete Data Sheet FPGA, 192 CLBS, 50000 GATES, PQFP144
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| File Size |
1,658.59K /
198 Page |
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Xilinx
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| Part No. |
XC3S100E XC3S1200E XC3S1600E
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| OCR Text |
...lternative to mask pro- grammed asics. fpgas avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional asics. also, fpga programmability permits design upgrades in the field with no hardware... |
| Description |
(XC3Sxx00E) Spartan-3E FPGA Family
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| File Size |
1,750.15K /
193 Page |
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Maxim
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| Part No. |
MAX3451E MAX3450E
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| OCR Text |
...nsceivers interface low-voltage asics with USB devices. The devices fully comply with USB 1.1 and USB 2.0 when operating at full (12Mbps) and low (1.5Mbps) speeds. The MAX3450E/MAX3451E/ MAX3452E operate with VL as low as +1.65V, ensuring c... |
| Description |
?à15kV ESD- Protected USB Transceivers
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| File Size |
381.53K /
16 Page |
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Atmel
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| Part No. |
ATL60
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| OCR Text |
...xt generation ATL60 Series CMOS asics are fabricated using a 0.6m drawn gate, oxide isolated, triple-level metal process. Extensive cell libraries are available and support the major CAD software tools. As with all Atmel ASIC families, cust... |
| Description |
The ATL60 series CMOS Gate Arrays are fabricated using a 0.6 micron drawn gate, oxide isolated, triple level metal process. Extensive cell libraries are available and support the major CAD software tools.
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| File Size |
109.90K /
14 Page |
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LSI Logic Corporation
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| Part No. |
ARM926EJ-S
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| OCR Text |
...erview 1.1.1 RapidChip Platform asics 1.1.2 CoreWare IP Program 1.1.3 RapidReadyTM Certification 1.1.4 RapidWorx Processor System for ARM926EJ-S Product Description 1.2.1 Processor System for ARM926EJ-S Overview 1.2.2 Processor System for A... |
| Description |
0.11 um Processor
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| File Size |
199.35K /
70 Page |
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Price and Availability
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