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Part No. |
CAT64LC20J CAT64LC40J CAT64LC10PI CAT64LC40SA CAT64LC40SI CAT64LC20SI CAT64LC20JI CAT64LC20PI
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Description |
18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write<br>36-Mbit ddr-ii sram 2-Word burst Architecture<br>9-Mbit QDR- II™ sram 2-Word burst Architecture<br>36-Mbit ddr-ii sram 2-Word burst Architecture (2.5 Cycle Read Latency)<br>36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined sram with NobL™ Architecture<br>36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through sram with NobL™ Architecture<br>SPI Serial EEPROM<br>4-Mbit (128K x 36) Pipelined Sync sram<br>9-Mbit (256K x 36/512K x 18) Pipelined sram<br>
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File Size |
87.91K /
9 Page |
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it Online |
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Cypress Semiconductor, Corp.<br>CYPRESS SEMICONDUCTOR CORP<br>
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Part No. |
CY7C1168V18-400bZXC CY7C1168V18-375bZXC CY7C1168V18-375bZC CY7C1166V18-400bZXC
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Description |
1M X 18 DDR sram, 0.45 ns, PbGA165 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FbGA-165<br>18-Mbit ddr-ii sram 2-Word burst Architecture (2.5 Cycle Read Latency) 1M X 18 DDR sram, 0.45 ns, PbGA165<br>2M X 8 DDR sram, 0.45 ns, PbGA165<br>
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File Size |
455.35K /
27 Page |
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it Online |
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Cypress Semiconductor, Corp.<br>
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Part No. |
CY7C1568KV18-550bZXC
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Description |
72-mbit ddr-ii sram 2-Word burst Architecture (2.5 Cycle Read Latency); Architecture: ddr-ii CIO, 2 Word burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR sram, 0.45 ns, PbGA165<br>
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File Size |
601.94K /
29 Page |
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it Online |
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Cypress Semiconductor, Corp.<br>
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Part No. |
CY7C1518KV18-300bZXC
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Description |
72-mbit ddr-ii sram 2-Word burst Architecture; Architecture: ddr-ii CIO, 2 Word burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR sram, 0.45 ns, PbGA165<br>
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File Size |
973.05K /
33 Page |
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it Online |
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Cypress Semiconductor, Corp.<br>CYPRESS SEMICONDUCTOR CORP<br>
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Part No. |
CY7C1568KV18-500bZXC CY7C1568KV18-500bZC CY7C1570KV18-500bZXC CY7C1570KV18-450bZXC
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Description |
72-mbit ddr-ii sram 2-Word burst Architecture (2.5 Cycle Read Latency); Architecture: ddr-ii CIO, 2 Word burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR sram, 0.45 ns, PbGA165<br>72-mbit ddr-ii sram 2-Word burst Architecture (2.5 Cycle Read Latency); Architecture: ddr-ii CIO, 2 Word burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 DDR sram, 0.45 ns, PbGA165<br>
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File Size |
611.30K /
30 Page |
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it Online |
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Price and Availability
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