| PART |
Description |
Maker |
| MC74F112 MC74F112D MC74F112J MC74F112N ON1232 |
1.2 to 5.5 V 10-A, 12-V Input Non-Isolated Wide-Adjust Module 10-DIP MODULE -40 to 85 F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP 双JK负边沿触发器
From old datasheet system
|
Motorola Mobility Holdings, Inc.
MOTOROLA[Motorola, Inc]
|
| SN74LS113D SN74LS113N SN54LS113J SN54LS113A |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
|
| SN74LS112D |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
Motorola, Inc
|
| HD74LS107A HD74LS107AFPEL HD74LS107AP |
Dual J-K Negative-edge-triggered Flip-Flops (with Clear)
|
Renesas Electronics Corporation
|
| 74F112 I74F112D I74F112N N74F112D N74F112N 74F112_ |
From old datasheet system
Dual J-K negative edge-triggered flip-flop
|
NXP Semiconductors
PHILIPS[Philips Semiconductors]
|
| IDT74LVC112A 74LVC112A_DS_87847 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
From old datasheet system
|
IDT
|
| IDT74LVC11 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5V TOLERANT I/O
|
IDT
|
| 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ 74LCX112 |
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
|
FAIRCHILD[Fairchild Semiconductor]
|
| 74ACT11112 |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 具有清零和预设功能的双路 J-K 下降沿触发器
|
Linear Technology, Corp.
|
| MC74F113D |
F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
MOTOROLA INC
|
| 74F114SC 74F114 74F114PC |
双JK负沿触发器与普通时钟和清除拖鞋
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
From old datasheet system
|
锁存
FAIRCHILD[Fairchild Semiconductor]
|
