| PART |
Description |
Maker |
| M2S56D40ATP75A M2S56D40ATP-75 M2S56D40ATP-10 M2S56 |
256M Double Data Rate Synchronous DRAM
|
MITSUBISHI[Mitsubishi Electric Semiconductor]
|
| GS8170DD36C-333 GS8170DD36C-250 GS8170DD36C-300 GS |
18Mb x2Lp CMOS I/O Double Data Rate SigmaRAM 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209
18Mb 1x2Lp CMOS I/O Double Data Rate SigmaRAM 35.71x2Lp的CMOS的I / O双数据速率SigmaRAM
|
GSI Technology, Inc.
|
| HY5DU56422DTP HY5DU56822DTP HY5DU56822DTP-J HY5DU5 |
256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) 32M X 8 DDR DRAM, 0.75 ns, PDSO66
|
Hynix Semiconductor Inc.
Hynix Semiconductor, Inc.
|
| K4D26323RA-GC |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| K4D26323AA-GL |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Data Sheet
|
Samsung Electronic
|
| DDR110-56T7RL DDR110-XXT7RL DDR110-27T7RL |
10-LINE 56 ohm OTHER TERMINATOR, PDSO24
DOUBLE DATA RATE TERMINATION NETWORK WITH DISABLE SWITCH 双倍数据速率终端网络具有禁用开
DOUBLE DATA RATE TERMINATION NETWORK WITH DISABLE SWITCH
|
STMicroelectronics N.V.
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| M13S128324A-2M |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M14D2561616A-2E |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| NT5DS4M32EG-5 NT5DS4M32EG-5G NT5DS4M32EG-6 |
1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL
|
NanoAmp Solutions, Inc.
|
| HYB25D512800AT-7F |
512Mbit Double Data Rate SDRAM
|
Infineon Technologies A...
|
| MT46V64M16 MT46V128M8 MT46V256M4 |
DOUBLE DATA RATE (DDR) SDRAM
|
MICRON[Micron Technology]
|
