| PART |
Description |
Maker |
| AS7C33512PFS16A |
3.3V 512K x 16/18 pipeline burst synchronous SRAM
3.3V 512K×16 Pipeline Burst Synchronous SRAM(3.3V 512K×16流水线脉冲同步静态RAM) 3.312k × 16管道爆裂同步SRAM的电压（3.3V12k × 16流水线脉冲同步静态内存）
|
Alliance Semiconductor, Corp.
|
| IS61NVP25636A-200TQI IS61NLP25636A-200B2I IS61NLP2 |
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 256K X 36 ZBT SRAM, 3.1 ns, PQFP100
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 256K X 36 ZBT SRAM, 3.1 ns, PBGA119
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 256K X 36 ZBT SRAM, 2.6 ns, PQFP100
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 256K X 36 ZBT SRAM, 2.6 ns, PBGA119
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 3.1 ns, PBGA165
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 2.6 ns, PBGA165
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 2.6 ns, PBGA119
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 3.1 ns, PBGA119
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 2.6 ns, PQFP100
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 3.1 ns, PQFP100
256K X 36 ZBT SRAM, 3.1 ns, PBGA165
|
Integrated Silicon Solution, Inc.
INTEGRATED SILICON SOLUTION INC
|
| AS7C3364PFS32A-133TQC AS7C3364PFS32A-133TQI |
3V 64K x 8/512K x 32 pipeline burst synchronous SRAM, 133MHz
|
Alliance Semiconductor
|
| IS61SPS51218T-133TQI IS61SPS51218T-150TQ IS61SPS51 |
512K X 18 CACHE SRAM, 3.8 ns, PBGA119
512K x 18 synchronous pipeline, single-cycle deselect static RAM
256K x 32 synchronous pipeline, single-cycle deselect static RAM
256K x 36 synchronous pipeline, single-cycle deselect static RAM
256K X 36 CACHE SRAM, 4 ns, PQFP100
512K X 18 CACHE SRAM, 4 ns, PQFP100
|
Integrated Silicon Solution Inc
|
| IS61NVP51218A IS61NVP51218A-200B2 IS61NVP51218A-20 |
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
|
ISSI[Integrated Silicon Solution, Inc]
|
| IS61NVVP25672-250B IS61NVVP25672-250BI IS61NVVP256 |
256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
|
ISSI[Integrated Silicon Solution, Inc]
|
| AS7C33512PFS18A AS7C33512PFS18AV.2.2 AS7C33512PFS1 |
Sync SRAM - 3.3V
From old datasheet system
3.3V 512K x 18 pipeline burst synchronous SRAM
|
ALSC
Alliance Semiconductor Corporation
|
| EUM6179MIR1 EUM6179AMIR1 EUM6179 |
512K x 36, 3.3V, Sync Burst Pipeline 单相全波电机风扇电机驱动
Single-Phase Full-Wave Motor Driver for Fan Motor
|
Eutech Microelectronics, Inc.
德信科技股份有限公司
Eutech Microelectronics Inc
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| IDT71T75602S133BG IDT71T75802S200BG IDT71T75802S20 |
512K x 36/ 1M x 18 2.5V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
2.5V 512K X 36 ZBT Synchronous 2.5V I/O PipeLine SRAM
512K x 36, 1M x 18 2.5V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
512K x 36, 1M x 18 2.5V Synchronous ZBT?/a> SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
BULK COAXIAL CABLE; RE-SHAPABLE VERSION OF PE-047SR
512K x 36, 1M x 18 2.5V Synchronous ZBTSRAMs 2.5V I/O, Burst Counter Pipelined Outputs 1M X 18 ZBT SRAM, 4.2 ns, PQFP100
High-Performance Current-Mode PWM Controller 8-SOIC -40 to 85 1M X 18 ZBT SRAM, 3.2 ns, PBGA119
512K x 36, 1M x 18 2.5V Synchronous ZBTSRAMs 2.5V I/O, Burst Counter Pipelined Outputs 1M X 18 ZBT SRAM, 3 ns, PQFP100
Current-Mode PWM Controller 14-SOIC -40 to 85 1M X 18 ZBT SRAM, 3.8 ns, PQFP100
Current-Mode PWM Controller 8-PDIP -40 to 85 1M X 18 ZBT SRAM, 3.5 ns, PQFP100
Current-Mode PWM Controller 8-SOIC -40 to 85 1M X 18 ZBT SRAM, 5 ns, PQFP100
|
IDT
Integrated Device Technology, Inc.
SRAM
|
| CY7C1372CV25-167AI CY7C1372CV25-167BGI CY7C1372CV2 |
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 2.8 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 2.8 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3.4 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3.4 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 12k × 36/1M × 18流水线的SRAM架构的总线延迟
CAP,Ceramic,10000pF,500VDC,10-% Tol,10% Tol,X7R-TC Code,-15,15%-TC,30ppm-TC RoHS Compliant: Yes
512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
|
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
|
|
