AT17LV256A-10JC - FPGA Configuration EEPROM Memory 2M X 1 CONFIGURATION MEMORY, PQCC44 5015 RR 19#16 PIN PLUG FPGA配置EEPROM存储 FPGA Configuration EEPROM Memory 4M X 1 CONFIGURATION MEMORY, PQCC44 FPGA Configuration EEPROM Memory 1M X 1 CONFIGURATION MEMORY, DSO8 FPGA Configuration EEPROM Memory 2M X 1 CONFIGURATION MEMORY, PQFP44 High Speed CMOS Logic Dual Monostable Multivibrators with Reset 16-TSSOP -55 to 125 FPGA配置EEPROM存储 High Speed CMOS Logic Dual Monostable Multivibrators with Reset 16-SOIC -55 to 125 高速CMOS逻辑可复位双重单稳态多谐振荡器 SOIC-16封装 工作温度55℃_125 FPGA Configuration EEPROM Memory FPGA配置EEPROM存储 高速CMOS逻辑可复位双重单稳态多谐振荡器 PDIP-16封装 工作温度55℃_125 5015 RR 19#16 SKT PLUG High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-PDIP -55 to 125 5015 RR 8#16 PIN PLUG L/C High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SO -55 to 125 PhotoMOS Relay; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Voltage:5V RoHS Compliant: No Connector assemblies, Ribbon (Flat); Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SOIC -55 to 125 High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-TSSOP -55 to 125 5015 RR 4#12 SKT PLUG High Speed CMOS Logic 4-Bit Parallel Access Register 16-TSSOP -55 to 125 High Speed CMOS Logic Dual 4-Input AND Gates 14-SOIC -55 to 125 High Speed CMOS Logic Dual 4-Input AND Gates 14-PDIP -55 to 125 HV7 33W WCDMA NH780HS

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