| PART |
Description |
Maker |
| MC100LVEL29DWR2 |
3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset 100LVEL SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO20
|
ON Semiconductor
|
| 5962F9863201VCC 5962F9863201V9A 5962F9863201VXC AC |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
Radiation Hardened Dual J-K Flip-Flop with Set and Reset 辐射硬化的设置和复位JK触发
|
Intersil Corporation
Intersil, Corp.
|
| ACTS74HMSR-02 |
Dual D Type Flip Flop with Set and Reset, Advanced Logic, CMOS; Temperature Range: -55°C to 125°C; Package: Die (Military Visual) ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14
|
Intersil, Corp.
|
| 74HC74DR2 74HC74DG |
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
ON Semiconductor
|
| SL74HC112 SL74HC112D SL74HC112N |
Dual J-K Flip-Flop with Set and Reset
|
System Logic Semiconduc...
SLS[System Logic Semiconductor]
|
| IN74HCT109 |
DUAL J-K FLIP-FLOP WITH SET AND RESET
|
INTEGRAL[Integral Corp.]
|
| IN74ACT109N IN74ACT109 IN74ACT109D |
DUAL J-K FLIP-FLOP WITH SET AND RESET
|
INTEGRAL[Integral Corp.]
|
| MC74HC74A |
Dual D Flip-Flop with Set and Reset
|
Motorola
|
| IN74ACT112N IN74ACT112 IN74ACT112D |
DUAL J-K FLIP-FLOP WITH SET AND RESET 双JK触发器与SET和RESET
|
INTEGRAL JOINT STOCK COMPANY
INTEGRAL[Integral Corp.]
|
| HCTS74MS HCTS74D HCTS74DMSR HCTS74HMSR HCTS74K HCT |
Radiation Hardened Dual-D Flip-Flop with Set and Reset
|
INTERSIL[Intersil Corporation]
|
| MC54_74HC74A MC54HC74AJ ON1495 |
DUAL D FLIP-FLOP WITH SET AND RESET
From old datasheet system
|
ON Semi
MOTOROLA[Motorola Inc]
|
