View AD5201_9064.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
FEATURES 256-Position, 2-Channel Potentiometer Replacement 10 k , 50 k , 100 k Power Shut-Down, Less than 5 A 2.7 V to 5.5 V Single Supply 2.7 V Dual Supply 3-Wire SPI-Compatible Serial Data Input Midscale Preset During Power-On APPLICATIONS Mechanical Potentiometer Replacement Stereo Channel Audio Level Control Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Automotive Electronics Adjustment
SHDN
2-Channel, 256-Position Digital Potentiometer AD5207
FUNCTIONAL BLOCK DIAGRAM
A1 W1 B1 A2 W2 B2
VDD VSS CS
RDAC1 REGISTER R
RDAC2 REGISTER R
LOGIC
POWERON RESET
AD5207
CLK SDI DGND
8 SDO
SERIAL INPUT REGISTER
GENERAL DESCRIPTION
The AD5207 provides dual channel, 256-position, digitally controlled variable resistor (VR) devices that perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5207 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance, between the A Terminal and the wiper or the B Terminal and the wiper. The fixed A-to-B terminal resistance of 10 k, 50 k or 100 k has a 1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs and avoids any make-before-break or breakbefore-make operation. Each VR has its own VR latch, which holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register, which is loaded from a standard 3-wire serial-input digital interface. Ten bits, to make up the data word, are required and clocked into the serial input register.
The first two bits are address bits. The following eight bits are the data bits that represent the 256 steps of the resistance value. The reason for two address bits instead of one is to be compatible with similar products such as AD8402 so that drop-in replacement is possible. The address bit determines the corresponding VR latch to be loaded with the data bits during the returned positive edge of CS strobe. A serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple VR applications without additional external decoding logic. An internal reset block will force the wiper to the midscale position during every power-up condition. The SHDN pin forces an open circuit on the A Terminal and at the same time shorts the wiper to the B Terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. The digital interface remains active during shutdown; code changes can be made to produce new wiper positions when the device is resumed from shutdown. The AD5207 is available in 1.1 mm thin TSSOP-14 package, which is suitable for PCMCIA applications. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +125C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD5207-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10 k , 50 k , 100 k
VB = 0, -40 C < TA < +125 C unless otherwise noted.)
Parameter DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential Nonlinearity2 Resistor Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance Nominal Resistance Match DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution Integral Nonlinearity4 Differential Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range5 Capacitance6 AX, BX Capacitance6 WX Shutdown Current7 Shutdown Wiper Resistance Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Single-Supply Range Power Dual-Supply Range Positive Supply Current Negative Supply Current Power Dissipation8 Power Supply Sensitivity, VDD Power Supply Sensitivity, VSS DYNAMIC CHARACTERISTICS6, 9 Bandwidth -3 dB Bandwidth -3 dB Bandwidth -3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Crosstalk10 Symbol Conditions Min Typ1 Max Unit
VERSION (V
DD
= 5 V, VSS = 0, VA = 5 V,
R-DNL R-INL R RAB/T RW R/RO
RWB, VA = NC RWB, VA = NC VAB = VDD, Wiper = No Connect IW = 1 V/R, VDD = 5 V Ch 1 to 2, VAB = VDD, TA = 25C
-1 -1.5 -30 500 50 0.2
+1 +1.5 +30 100 1
LSB LSB % ppm/C %
N INL DNL VW/T VWFSE VWZSE VA, B, W CA,B CW IA_SD RW_SD ICM VIH VIL VIH VIL VOH VOL IIL CIL VDD RANGE VDD/SS RANGE IDD ISS PDISS PSS PSS BW_10 k BW_50 k BW_100 k THDW tS eN_WB CT
VDD = 5 V, VSS = 0 V Code = 80H Code = FFH Code = 00H |VDD| + |VSS| 5.5 V f = 1 MHz, Measured to GND, Code = 80H f = 1 MHz, Measured to GND, Code = 80H VA = VDD, VB = 0 V, SHDN = 0 VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V VA = VB = VDD/2 VDD = 5 V, VSS = 0 V VDD = 5 V, VSS = 0 V VDD = 3 V, VSS = 0 V VDD = 3 V, VSS = 0 V RL = 1 k to VDD IOL = 1.6 mA, VDD = 5 V VIN = 0 V or 5 V
8 -1.5 -1 15 -1.5
+1.5 +1
Bits LSB LSB ppm/C LSB LSB V pF pF A nA V V V V V V A pF V V A A mW %/% %/% kHz kHz kHz % s nVHz dB
+1.5 VSS 45 70 5 200 1 2.4 0.8 2.1 0.6 VDD - 0.1 0.4 10 10 VDD
VSS = 0 V VIH = VDD or VIL = GND, VSS = 0 V VIH = VDD or VIL = GND VSS = -2.5 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = 5 V 10%, VSS = 0 V, Code = 80H VSS = -2.5 V 10%, VDD = 2.5 V, Code = 80H RAB = 10 k RAB = 50 k RAB = 100 k VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k RAB = 10 k/50 k/100 k, 1 LSB Error Band RWB = 5 k, f = 1 kHz, RS = 0 VA = 5 V, VB = 0 V
2.7 2.2
5.5 2.7 40 40 0.2 0.01 0.03 600 125 71 0.003 2/9/18 9 -65
-2-
REV. 0
AD5207
Parameter INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 11 Input Clock Pulsewidth Data Setup Time Data Hold Time CLK to SDO Propagation Delay12 CS Setup Time CS High Pulsewidth CLK Fall to CS Fall Hold Time CLK Fall to CS Rise Hold Time CS Rise to Clock Rise Setup Symbol Conditions Min Typ1 Max Unit
tCH, tCL tDS tDH tPD tCSS tCSW tCSH0 tCSH1 tCS1
Clock Level High or Low
RL = 1 k to 5 V, CL < 20 pF
10 5 5 1 10 10 0 0 10
25
ns ns ns ns ns ns ns ns ns
NOTES 1 Typicals represent average readings at 25C and VDD = 5 V, VSS = 0 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = 5 V, VSS = 0 V. 3 VAB = VDD, Wiper (VW) = No connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions. 5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A X terminals. All A X terminals are open-circuited in shut-down mode. 8 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use V DD = 5 V, VSS = 0 V. 10 Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. 11 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using V DD = 5 V. 12 Propagation delay depends on value of V DD, RL, and CL; see applications text. The AD5207 contains 474 transistors. Die Size: 67 mil x 69 mil, 4623 sq. mil. Specifications subject to change without notice.
1 SDI 0 1 CLK 0 1 CS 0 VOUT RDAC REGISTER LOAD A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 1a. Timing Diagram
SDI (DATA IN) 1 Ax OR Dx 0 1 A'x OR D'x 0 Ax OR Dx
tDS
tDH
SDO (DATA OUT)
A'x OR D'x
tPD_MAX tCH
1 CLK 0
tCS1 tCL tCSH1 tCSW tS
tCSH0
1 CS 0 VDD 0V
tCSS
VOUT
1LSB ERROR BAND 1LSB
Figure 1b. Detail Timing Diagram
REV. 0
-3-
AD5207
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C, unless otherwise noted)
PIN FUNCTION DESCRIPTIONS
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0, -3 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD IMAX2 (A, B, W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Digital Inputs and Output Voltage to GND . . 0 V, VDD + 0.3 V Operating Temperature Range . . . . . . . . . . -40C to +125C Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C Thermal Resistance3 JA, TSSOP-14 . . . . . . . . . . . . . 206C/W
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Max current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W Terminals at a given resistance. Please refer to TPC 22 for detail. 3 Package Power Dissipation = (T J Max-TA)/JA.
Pin Mnemonic Description 1 2 3 4 5 6 VSS B2 A2 W2 DGND SHDN Negative Power Supply, specified for operation from 0 V to -2.7 V. Terminal B of RDAC#2. Terminal A of RDAC#2. Wiper, RDAC#2, addr = 12 Digital Ground. Active Low Input. Terminal A open-circuit and Terminal B shorted to Wiper. Shutdown controls both RDACs #1 and #2. Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the address bit, and loaded into the corresponding RDAC register. Serial Data Input. MSB is loaded first. Serial Data Output. Open Drain transistor requires pull-up resistor. Serial Clock Input. Positive Edge Triggered. Positive Power Supply. Specified for operation at 2.7 V to 5.5 V. Wiper, RDAC #1, addr = 02. Terminal A of RDAC #1. Terminal B of RDAC #1.
Table I. Serial-Data Word Format
7
CS
8 9 10 11 12 13 14
SDI SDO CLK VDD W1 A1 B1
PIN CONFIGURATION
VSS 1 B2 2 A2 3
14 B1 13 A1
AD5207
12 W1
W2 4 TOP VIEW 11 VDD (Not to Scale) 10 DGND 5 CLK SHDN 6 CS 7
9 8
ADDR B9 B8 A1 29 A0 28
B7
B6
B5 D5
DATA B4 B3 D4 D3
B2 D2
B1 D1
B0 D0 LSB 20
SDO SDI
D7 D6 MSB 27
NOTES ADDR(RDAC1) = 00; ADDR(RDAC2 = 01). Data loads B9 first into SDI pin.
ORDERING GUIDE
Model AD5207BRU10-REEL7 AD5207BRU50-REEL7 AD5207BRU100-REEL7
k 10 50 100
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description TSSOP-14 TSSOP-14 TSSOP-14
Package Option RU-14 RU-14 RU-14
Qty Per Container 1,000 1,000 1,000
Branding Information* B10 B50 B100
*Three lines of information appear on the device. Line 1 lists the part number; Line 2 includes branding information and the ADI logo, and Line 3 contains the date code YYWW.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5207 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. 0
Typical Performance Characteristics-AD5207
0.20 VDD = 5.5V, V SS = 0V 0.15 0.10 0.3 0.2 0.1 0.4 VDD = 5.5V, V SS = 0V
RDNL - LSB
INL - LSB
0 32 64 96 128 160 CODE - Decimal 192 224 256
0.05 0.00 0.05 0.10 0.15 0.20
0.0 -0.1 -0.2 -0.3 -0.4
0
32
64
96 128 160 CODE - Decimal
192
224
256
TPC 1. 10 k RDNL vs. Code
TPC 4. 10 k INL vs. Code
0.20 VDD = 5.5V, V SS = 0V 0.15 0.10
1.0
IDD @ VDD/V SS = 5V/0V
IDD/I SS - mA
RINL - LSB
0.05 0.00
0.1
IDD @ VDD/V SS =
2.5V
-0.05 -0.10 -0.15 -0.20
0.01
ISS @ VDD/V SS =
2.5V IDD @ V DD/V SS = 3V/0V
0
32
64
96 128 160 CODE - Decimal
192
224
256
0.001 0.0
1.0
2.0
VIH - V
3.0
4.0
5.0
TPC 2. 10 k RINL vs. Code
TPC 5. Supply Current vs. Logic Input Voltage
0.3 VDD = 5.5V, V SS = 0V 0.2
20 18 VIL = VSS VIH = VDD
IDD SUPPLY CURRENT - A
16 14 12 10 8 6 4 VDD = 2.7V VDD = 5.5V
0.1
DNL - LSB
0.0
-0.1
-0.2 2 -0.3 0 -40
0
32
64
96 128 160 CODE - Decimal
192
224
256
-20
0
20 40 TEMPERATURE - C
60
80
100
TPC 3. 10 k DNL vs. Code
TPC 6. Supply Current vs. Temperature
REV. 0
-5-
AD5207
45 VDD = 5.5V 40
900 800 700 1000 CODE 55H
IA_SD SHUTDOWN CURRENT - nA
35 30
IDD/I SS - A
600 500 400 300 200 100
ISS @ VDD/V SS =
2.5V
25 20 15 10 5
IDD @ VDD/V SS =
2.5V
IDD @ V DD/V SS = 5V/0V IDD @ VDD/V SS = 3V/0V
0 -40
-20
0
20 40 60 80 TEMPERATURE - C
100
120
0 10k
100k 1M FREQUENCY - Hz
10M
TPC 7. Shutdown Current vs. Temperature
TPC 10. 10 k Supply Current vs. Clock Frequency
160 140 120 100
80
CODE = 80H, VA = VDD, VB = 0V +PSRR @ VDD = 5V DC 10% p-p AC
60
80 60 40 20 0 0
VDD = 3V
PSRR - dB
VDD = 5V
RON -
40
+PSRR @ VDD = 3V DC
10% p-p AC
20
-PSRR @ VDD = 3V DC 10% p-p AC
1
2
3
VSUPPLY - V
4
5
6
0 100
1k
10k FREQUENCY - Hz
100k
1M
TPC 8. Wiper ON Resistance vs. VSUPPLY
TPC 11. Power Supply Rejection Ratio vs. Frequency
1000 900 800 700 CODE FFH
0 -6 -12 -18 DATA = 80 H DATA = 40 H DATA = 20 H DATA = 10 H DATA = 08 H DATA = 04 H DATA = 02 H -42 DATA = 01 H VDD = +2.7V VA VSS = -2.7V VA = 100mV rms TA = 25 C -48
IDD/I SS - A
500 400 300 200
ISS @ VDD/V SS = IDD @ VDD/V SS = IDD @ VDD/V SS = 5V/0V IDD @ VDD/V SS = 3V/0V
2.5V
GAIN - dB
600
-24 -30 -36
2.5V
100 0 10k
-54 -60 1k
OP42
100k 1M FREQUENCY - Hz
10M
10k 100k FREQUENCY - Hz
1M
TPC 9. 10 k Supply Current vs. Clock Frequency
TPC 12. 10 k Gain vs. Frequency vs. Code
-6-
REV. 0
AD5207
0 -6 -12 -18 DATA = 80 H DATA = 40 H DATA = 20 H DATA = 10 H
-5.99 -6.00 -6.01 -6.02
10k VDD = +2.7V VSS = -2.7V VA = 100mV rms DATA = 80 H TA = 25 C 50k 100k
GAIN - dB
-30 -36 -42 -48 -54 -60 1k
VDD = +2.7V VA VSS = -2.7V VA = 100mV rms TA = 25 C
DATA = 08 H DATA = 04 H DATA = 02 H
GAIN - dB
-24
-6.03 -6.04 -6.05 -6.06
DATA = 01 H
-6.07 -6.08
VA VB = 0V OP42
OP42
10k 100k FREQUENCY - Hz
1M
-6.09 100
1k
10k FREQUENCY - Hz
100k
TPC 13. 50 k Gain vs. Frequency vs. Code
TPC 16. Normalized Gain Flatness vs. Frequency
0 -6 -12 -18 DATA = 80 H DATA = 40 H DATA = 20 H
GAIN - dB
-24 -30 -36 -42 -48 -54 -60 1k
VDD = +2.7V VA VSS = -2.7V VA = 100mV rms TA = 25 C
DATA = 08 H DATA = 04 H DATA = 02 H DATA = 01 H
OP42
10k 100k FREQUENCY - Hz
1M
TPC 14. 100 k Gain vs. Frequency vs. Code
TPC 17. One Position Step Change at Half Scale
6 4 2 0 10k
GAIN - dB
-2 -4 -6 -8 -10 -12 -14 1k VDD = 2.7V 2.7V VSS = 0V 6 VA = 100mV rms DATA = 80 H 1.5V TA = 25 C 100k 50k
OP42
10k 100k FREQUENCY - Hz
1M
VIN (5mV/DIV)
VOUT (50mV/DIV)
VW (10mV/DIV)
DATA = 10 H
TPC 15. -3 dB Bandwidth
TPC 18. Large Signal Settling Time
REV. 0
-7-
AD5207
2500
RHEOSTAT MODE TEMPCO - ppm/ C
2000
VW (10mV/DIV)
1500
1000
500
0
500
0
32
64
96
128 160 CODE - Decimal
192
224
256
TPC 19. Digital Feedthrough vs. Time
TPC 21. RWB/T Rheostat Mode Temperature Coefficient
120
100.0
POTENTIOMETER MODE TEMPCO - ppm/ C
100
THEORETICAL IMAX - mA
80 60 40 20 0 -20
40
IWB_MAX 10.0
RAB = 10k 1.0
RAB = 50k
0.1
0 32 64 96 128 160 CODE - Decimal 192 224 256
0
32
64
128 96 160 CODE - Decimal
192
224
256
TPC 20. VWB /T Potentiometer Mode Temperature Coefficient
TPC 22. IMAX vs. Code
-8-
REV. 0
AD5207
OPERATION
The AD5207 provides a dual channel, 256-position digitally controlled variable resistor (VR) device. The terms VR, RDAC, and digital potentiometer are sometimes used interchangeably. Changing the programmable VR settings is accomplished by clocking in a 10-bit serial data word into the SDI (Serial Data Input) pin. The format of this data word is two address Bits, A1 and A0. With A1 and A2 are first and second bits respectively, followed by eight data bits B7-B0 with MSB first. Table I provides the serial register data word format. See Table III for the AD5207 address assignments to decode the location of VR latch receiving the serial register data in Bits B7 through B0. VR settings can be changed one at a time in random sequence. The AD5207 presets to a midscale during power-on condition. AD5207 contains a power shutdown SHDN pin. When activated in logic low. Terminals A on both RDACs will be open-circuited while the wiper terminals WX are shorted to BX. As a result, a minimum amount of leakage current will be consumed in both RDACs, and the power dissipation is negligible. During the shutdown mode, the VR latch settings are maintained. Thus the previous resistance values remain when the devices are resumed from the shutdown.
DIGITAL INTERFACING
The serial-data-output (SDO) pin contains an open drain n-channel FET. This output requires a pull-up resistor in order to transfer data to the next package's SDI pin. The pull-up resistor termination voltage may be larger than the VDD supply of the AD5207 SDO output device, e.g., the AD5207 could operate at VDD = 3.3 V and the pull-up for interface to the next device could be set at 5 V. This allows for daisy chaining several RDACs from a single processor serial-data line. The clock period may need to be increased when using a pull-up resistor to the SDI pin of the following devices in series. Capacitive loading at the daisy chain node SDO-SDI between devices may add time delay to subsequent devices. User should be aware of this potential problem in order to successfully achieve data transfer. See Figure 3. When configuring devices for daisy-chaining, the CS should be kept low until all the bits of every package are clocked into their respective serial registers, ensuring that the address bit and data bits are in the proper decoding location. This requires 20 bits of address and data complying with the data word in Table I if two AD5207 RDACs are daisy chained. During shutdown SHDN, the SDO output pin is forced to OFF (logic high state) to disable power dissipation in the pull-up resistor. See Figure 4 for equivalent SDO output circuit schematic.
+V
The AD5207 contains a standard three-wire serial input control interface. The three inputs are clock (CLK), chip select (CS), and serial data input (SDI). The positive edge-sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. Figure 2 shows more detail of the internal digital circuitry. When CS is low, the clock loads data into the serial register on each positive clock edge; see Table II.
AD5207
CS RDAC LATCH #1 A1 W1 B1
AD5207
C SDI SDO
RP 2k SDI
AD5207
SDO
CS
CLK
CS
CLK
Figure 3. Daisy-Chain Configuration Using SDO
Table II. Input Logic Control Truth Table
VDD
CLK L P
CS L L
SHDN H H
Register Activity No SR effect, enables SDO pin. Shift one bit in from the SDI pin. MSB first. The tenth previously entered bit is shifted out of the SDO pin. Load SR data into RDAC latch based on A0 decode (Table III). No Operation. Open circuits all resistor A Terminals, connects W to B, turns off SDO output transistor.
CLK
X
EN SDO A0 SER REG D7 D6 D5 D4 D3 D2 D1 D0 POWER-ON RESET SHDN ADDR DEC
P H H
H H L
X X
RDAC LATCH #2 A2 W2 B2 VSS
SDI
NOTE P = positive edge, X = don't care, SR = shift register.
Table III. Address Decode Table
A1 0 0
A0 0 1
Latch Loaded RDAC #1 RDAC #2
Figure 2. Block Diagram
REV. 0
-9-
AD5207
The data setup and data hold times in the specification table determine the data valid time requirements. The last ten bits of the data word entered into the serial register are held when CS returns high and any extra bits are ignored. At the same time, when CS goes high, it gates the address decoder enabling one of two positive edge-triggered AD5207 RDAC latches; see Figure 5 detail.
SHDN CS SERIAL REGISTER SDO D Q RDAC LATCH AND DECODER R S Bx INTERNAL RS SHDN RS D7 D6 D5 D4 D3 D2 D1 D0 Ax
RS
RS Wx
SDI
CK RS CLK
Figure 4. Detail SDO Output Schematic of the AD5207
Figure 8. Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
The target RDAC latch is loaded with the last eight bits of the data word to complete one RDAC update. For AD5207, it cannot update both channels simultaneously and therefore, two separate 10-bit data words must be clocked in to change both VR settings.
AD5207
CS ADDR DECODE RDAC1 RDAC2
CLK SDI SERIAL REGISTER
Figure 5. Equivalent Input Control Logic
All digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figures 6 and 7. Applies to digital input pins CS, SDI, SDO, SHDN, and CLK. Digital input level for Logic 1 can be anywhere from 2.4 V to 5 V regardless of whether it is in single or dual supplies.
340 DIGITAL PIN
The nominal resistance of the RDAC between Terminals A and B is available with values of 10 k, 50 k, and 100 k. The last few digits of the part number determine the nominal resistance value, e.g., 10 k = 10; 50 k = 50; and 100 k = 100. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B Terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assume a 10 k part is used, the wiper's first connection starts at the B Terminal for data 00H. Since there is a 45 wiper contact resistance, such connection yields a minimum of 45 resistance between Terminals W and B. The second connection is the first tap point corresponds to 84 (RWB = RAB/256 + RW = 39 + 45 ) for data 01H. The third connection is the next tap point representing 123 (39 x 2 + 45) for data 02H and so on. Each LSB value increase moves the wiper up the resistor ladder until the last tap point is reached at 10006 (RAB - 1 LSB + RW). Figure 8 shows a simplified diagram of the equivalent RDAC circuit. The general equation determining the programmable output resistance between W and B is: D (1) x RAB + RW 256 where D is the data contained in the 8-bit RDAC latch, and RAB is the nominal end-to-end resistance. For example, RAB =10 k, A Terminal can be open-circuit or tied to W. The following output resistance RWB will be set for the following RDAC latch codes. RWB ( D ) =
LOGIC
VSS
Figure 6. ESD Protection of Digital Pins
A,B,W
VSS
Figure 7. ESD Protection of Resistor Terminals
-10-
REV. 0
AD5207
Table IV.
D (DEC) 255 128 1 0
RWB () 10006 5045 84 45
Output State Full-Scale (RAB - 1 LSB + RW) Midscale 1 LSB Zero-Scale (Wiper Contact Resistance)
position of the potentiometer divider. Since AD5207 is capable for dual supplies, the general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW ( D ) = D 256 - D VA + VB 256 256 (3)
Note that in the zero-scale condition a finite wiper resistance of 45 is present. Care should be taken to limit the current flow between W and B in this state to a maximum current of no more than 5 mA. Otherwise, degradation or possibly destruction of the internal switch contacts can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and Terminal A also produces a digitally controlled resistance RWA. When these terminals are used, the B Terminal should be let open or tied to the wiper terminal. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general equation for this operation is: 256 - D (2) x RAB + RW 256 For example, when RAB = 10 k, B terminal is either open or tied to W, the following output resistance, RWA, will be set for the following RDAC latch codes.
Table V.
Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent on the ratio of RWA and RWB and not the absolute values; therefore, the drift reduces to 15 ppm/C. There is no voltage polarity constraint between Terminals A, B, and W as long as the terminal voltage stays within VSS < VTERM < VDD.
RDAC CIRCUIT SIMULATION MODEL
RWA ( D ) =
The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider the -3 dB bandwidth of the AD5207BRU10 (10 k resistor) measures 600 kHz at half scale. TPC 16 provides the large signal BODE plot characteristics of the three available resistor versions 10 k and 50 k. The gain flatness versus frequency graph, TPC 16, predicts filter applications performance. A parasitic simulation model has been developed and is shown in Figure 9. Listing I provides a macro model net list for the 10 k RDAC:
RDAC 10k A B CA CA = 45pF CW 70pF CB CB = 45pF
D (DEC) 255 128 1 0
RWA () 84 5045 10006 10045
Output State Full-Scale (RAB/256 + RW) Midscale 1 LSB Zero-Scale
W
Figure 9. RDAC Circuit Simulation Model for RDAC = 10 k
Listing I. Macro Model Net List for RDAC
The typical distribution of RAB from channel to channel matches within 1%. Device-to-device matching is process-lot dependent and is possible to have 30% variation. The change in RAB with temperature has a 500 ppm/C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
.PARAM D=255, RDAC=10E3 * .SUBCKT DPOT (A,W) * CA A 0 45E-12 RAW A W {(1-D/256)*RDAC+50} CW W 0 70E-12 RBW W B {D/256*RDAC+50} CB B 0 45E-12 * .ENDS DPOT
The digital potentiometer easily generates an output voltage proportional to the input voltage. Let's ignore the effect of the wiper resistance for the moment. For example, when connecting A Terminal to 5 V and B Terminal to ground, it produces a programmable output voltage at the wiper starting at zero volts up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256
REV. 0
-11-
AD5207
TEST CIRCUITS
Figures 10 to 18 define the test conditions used in product Specification table.
DUT A V+ B W VMS V+ = VDD 1 LSB = V+/2N
OFFSET GND VIN W
5V
OP279
VOUT
A
DUT
B
OFFSET BIAS
Figure 10. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
NO CONNECT DUT A W B VMS IW
Figure 15. Noninverting Gain Test Circuit
A W VIN OFFSET GND DUT B 2.5V
+15V
OP42 -15V
VOUT
Figure 11. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure 16. Gain vs. Frequency Test Circuit
DUT DUT VMS2 A W B VMS1 VW IW = VDD/R NOMINAL B W ISW
RSW =
0.1V ISW
H
CODE =
+ 0.1V -
RW = [VMS1 - V MS2]/IW
VSS TO VDD
Figure 12. Wiper Resistance Test Circuit
Figure 17. Incremental ON Resistance Test Circuit
NC
VA VDD V+ B VMS
VDD DUT A W GND B VCM ICM
A W
V+ = VDD
10% VMS VDD
VSS
PSRR (dB) = 20 LOG PSS (%/%) = VMS% VDD%
NC NC = NO CONNECT
Figure 13. Power Supply Sensitivity Test Circuit (PSS, PSSR)
A DUT B 5V W VIN OFFSET GND OFFSET BIAS OP279 VOUT
Figure 18. Common-Mode Leakage Current Test Circuit
Figure 14. Inverting Gain Test Circuit
-12-
REV. 0
AD5207
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE
Number of VRs per Package 1 Terminal Voltage Range 3 V, +5.5 V 5.5 V 15 V, +28 V 3 V, +5.5 V 5.5 V 5 V, +15 V 3 V, +5.5 V 3 V, +5.5 V 3 V, +5.5 V 5.5 V 3 V, +5.5 V 3 V, +5.5 V 3 V, +5.5 V 3 V, +5.5 V 5 V, +15 V 5.5 V 3 V, +5.5 V 3 V, +5.5 V 5.5 V 3 V, +5.5 V Interface Data Control 3-Wire Nominal Resistance (k ) 10, 50 Resolution (Number of Wiper Positions) 33 Power Supply Current (IDD) 40 A 40 A 100 A 40 A 5 A 60 A 50 A 20 A 80 A 5 A 40 A 20 A 20 A 50 A 60 A 5 A 20 A 60 A 5 A 60 A
Part Number AD5201
Packages SOIC-10 PDIP, SO-8, SOIC-8 PDIP-14, SOL-16, TSSOP-14 SOIC-10 SO-8 TSSOP-14
Comments Full AC Specs, Dual Supply, Pwr-On-Reset, Low Cost No Rollover, Pwr-On-Reset Single +28 V or Dual 15 V Supply Operation Full AC Specs, Dual Supply, Pwr-On-Reset Full AC Specs 15 V or 5 V, TC < 50 ppm/C I2C-Compatible, TC < 50 ppm/C Nonvolatile Memory, Direct Program, I/D, 6 dB Settability No Rollover, Stereo, Pwr-OnReset, TC < 50 ppm/C Full AC Specs, nA Shutdown Current Full AC specs, Dual Supply, Pwr-On-Reset, SDO Nonvolatile Memory, Direct Program, I/D, 6 dB Settability Nonvolatile Memory, Direct Program, TC < 50 ppm/C I2C-Compatible, TC < 50 ppm/C 15 V or 5 V, Pwr-OnReset, TC < 50 ppm/C Full AC Specs, nA Shutdown Current Nonvolatile Memory, Direct Program, I/D, 6 dB Settability Full AC Specs, Dual Supply, Pwr-On-Reset Full AC Specs, nA Shutdown Current Full AC Specs, Dual Supply, Pwr-On-Reset
AD5220 AD7376
1 1
Up/Down 3-Wire
10, 50, 100 10, 50, 100, 1000
128 128
AD5200
1
3-Wire
10, 50
256
AD8400 AD5260
1 1
3-Wire 3-Wire
1, 10, 50, 100 20, 50, 200
256 256
AD5241
1
2-Wire
10, 100, 1000
256
SO-14, TSSOP-14
AD5231* 1
3-Wire
10, 50, 100
1024
TSSOP-16
AD5222
2
Up/Down
10, 50, 100, 1000
128
SO-14, TSSOP-14
AD8402 AD5207
2 2
3-Wire 3-Wire
1, 10, 50, 100 10, 50, 100
256 256
PDIP, SO-14, TSSOP-14 TSSOP-14
AD5232* 2
3-Wire
10, 50, 100
256
TSSOP-16
AD5235* 2
3-Wire
25, 250
1024
TSSOP-16
AD5242
2
2-Wire
10, 100, 1000
256
SO-16, TSSOP-16
AD5262* 2
3-Wire
20, 50, 200
256
TSSOP-16
AD5203
4
3-Wire
10, 100
64
PDIP, SOL-24, TSSOP-24 TSSOP-16
AD5233* 4
3-Wire
10, 50, 100
64
AD5204
4
3-Wire
10, 50, 100
256
PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24
AD8403
4
3-Wire
1, 10, 50, 100
256
AD5206
6
3-Wire
10, 50, 100
256
*Future product, consult factory for latest status. Latest Digital Potentiometer Information available at www.analog.com/support/standard_linear/selection_guides/dig_pot.html
REV. 0
-13-
AD5207
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
14-Lead TSSOP (RU-14)
0.201 (5.10) 0.193 (4.90)
14
8
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 7
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
-14-
REV. 0
-15-
-16-
C01885-1.5-4/01(0)
PRINTED IN U.S.A.

▲Up To Search▲

Price & Availability of AD5201

	To Download AD5201 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .