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| MITSUBISHI M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS DESCRIPTION The M62370GP is a CMOS semiconductor IC,containing 36 channels of 8-bit D-A converters.It is operable with a low supply voltage between 2.7~3.6V,and is easy to use due to serial data input,and 3-pin(DI,CLK,LD)connection with microcomputer.The IC also contains Do pin terminal,enabling cascade connection,and therefore is suitable for automatic control in combination with a microcomputer. PIN CONFIGURATION (TOP VIEW) FEATURES *Operable with a low voltage between 2.7~3.6V *16-bit serial data input(connected via 3 pins:DI,CLK,LD) *36 channels built-in of 8-bit D-A converter *6 channels of D-A converters capable of selecting and outputting 4 data stored in each converter,through 2 control terminals DI CLK LD Do GND C0 Vss1 VDD1 Ao12 Ao13 Ao14 Ao15 Ao35 Ao34 Ao33 Ao32 Vss2 VDD2 C1 Vcc Ao31 Ao30 Ao29 Ao28 APPLICATION Digital-analog conversion in industrial or home-use electronic equipment. Automatic control in combination with EEPROM and microcomputer(Substitute for conventional semi-fixed resistor) Outline 48P6D-A BLOCK DIAGRAM VCC 29 GND 5 CLK DI 2 16-BIT SHIFT REGISTER 1 D15 D14 D13 D12 D11 D10 D9 D8 D5 D4 D3 D2 D1 D0 4 Do 8 DECODER 3 LD 8-BIT LATCH 8-BIT LATCH X 4 8-BIT LATCH X 4 8-BIT LATCH X 4 VDD1 8 D-A Vss1 7 D-A D-A D-A DATA CONTROL 6 Co 30 C1 38 Ao1 21 Ao24 36 Ao35 37 Ao36 31 32 VDD2 Vss2 MITSUBISHI ELECTRIC ( 1/5) MITSUBISHI M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS EXPLANATION OF TERMINALS Pin No. 1 4 2 3 38 48 9 28 33 37 29 5 6 30 8 7 31 32 Symbol DI Do CLK LD Ao1 Ao11 Ao12 Ao31 Ao32 Ao36 VCC GND C0 C1 VDD1 VSS1 VDD2 VSS2 Power supply terminal GND terminal Data sslect signal input terminal 1 for channel No.31 through 36 Data select signal input terminal 2 for channel No.31 through 36 Upper reference voltage input terminal and power supply to operational amplifier for channel No.1 through 24 Lower reference voltage input terminal for channel No.1 through 24 Upper reference voltage input terminal and power supply to operational amplifier for channel No.25 through 36 Lower reference voltage input terminal for channel No.25 through 36 Function Serial data input terminal to input 16-bit long ssrial data Terminal to output MSB data of 16-bit shift register Shift clock input terminal.Input signal at DI pin is input to 16-bit shift register at rise of shift clock pulse When H-level signal is input to this terminal,the value stored in 16-bit shift register is loaded in decoder and D-A converter output register 8-bit D-A converter output terminal BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS Vcc 29 CLK 2 16-BIT SHIFT REGISTER DI 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 4 Do GND 5 ADDRESS DECODER (8) 1234 (4) 3 LD ............ 1 VDD1 8 Vss1 7 8-BIT LATCH ............ 8-BIT LATCH (4) ............ (4) 36 ............ 6 DATA CONTROL 30 C1 C0 8-BIT LATCH X 4 SEL 8-BIT LATCH X 4 SEL 8-BIT D-A CONVERTER 30 8-BIT D-A CONVERTER 31 DAC - DAC - - - 38 Ao1 27 Ao30 28 Ao31 37 Ao36 31 VDD2 32 Vss2 MITSUBISHI ELECTRIC ( 2/5) MITSUBISHI M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS DIGITAL DATA FORMAT FIRST LSB LAST MSB DAC DATA D8 0 1 0 1 D9 0 0 1 1 1 1 D4 0 0 0 1 1 0 0 0 0 0 1 1 D10 0 0 0 0 1 1 D3 0 0 0 1 1 0 0 0 1 1 D11 0 0 0 0 1 1 D2 0 0 0 1 1 0 1 1 0 0 D12 0 0 0 0 1 1 D1 0 0 1 1 1 0 0 0 1 1 D13 0 0 0 0 1 1 D0 0 1 0 0 1 0 0 1 0 1 D14 0 0 0 0 1 1 D15 0 0 0 0 1 1 DAC SELECT DATA D-A output (VrefU-VrefL) / 256 X 1 +VrefL (VrefU-VrefL) / 256 X 2 +VrefL (VrefU-VrefL) / 256 X 3 +VrefL (VrefU-VrefL) / 256 X 4 +VrefL (VrefU-VrefL) / 256 X 255 +VrefL VrefU Ao31 through Ao36 data selected Address 0 selected Address 1 selected Address 2 selected Address 3 selected 0 1 D5 0 0 0 0 0 1 1 1 DAC selection Don`t care Ao1 selection Ao2 selection Ao30 selection Ao31(0) selection Ao32(0) selection Ao36(0) selection Ao31(1) selection Ao36(1) selection Ao31(2) selection C0 0 0 1 1 C1 0 1 0 1 * VrefU=VDD1,VDD2 VrefL=Vss1,Vss2 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 1 Ao36(2) selection Ao31(3) selection Ao36(3) selection Don`t care Don`t care 1 1 1 1 0 0 1 1 1 1 TIMING CHART (MODEL) LSB DI D0 D1 D2 D3 D13 D14 MSB D15 CLK LD D-A OUTPUT MITSUBISHI ELECTRIC ( 3/5) MITSUBISHI M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS ABSOLUTE MAXIMUM RATINGS(Ta=25C,unless otherwise noted) Symbol Vcc Vo Pd K Topr Tstg Parameter Supply voltage Output voltage Power dissipation Terminal derating Operating temperature Storage temperature Ta25C Conditions Ratings -0.3~+7.0 -0.3~Vcc+0.3 400 4 -20~+85 -40~+125 Unit V V mW mW/C C C ELECTRICAL CHARACTERISTICS Digital part(VCC=+3V10%, VCC=VDD,Ta=-20 ~ +85C,unless otherwise noted) Symbol VCC Icc IILK VIL VIH VOL VOH Parameter Supply voltage Circuit current Input leak current Input low voltage Input high voltage Output low voltage Output high voltage IOL=2.5mA IOH=-400A VCC-0.4 CLK=1MHz operation,Vcc=3V,IAO=0A -10 2.4 0.4 Test conditions Min. 2.7 Limits Typ. 3.0 1.0 10 0.6 Max. 5.5 Unit V mA A V V V V Note.Standard value is at Ta=25C Analog part(VCC=+3V10%, VCC=VDD,Ta=-20 ~ +85C,unless otherwise noted) Symbol IDD VDD Vss VAO IAO SDL SL SZERO SFULL Co Ro Parameter Current dissipation D-A converter upper reference voltage range D-A converter lower reference voltage range IAO=100A Buffer amplifier output voltage range IAO=+300A -200A Upper saturation voltage=0.4V Buffer amplifier output driving Lower saturation voltage=0.3V range Differential nonlinearity error Vcc=2.700V Nonlinearity error VDD=2.700V Zero code error Vss=0.050V No load(IAO=0) Full scale error Output capacitative load Buffer amplifier output impedance 50 2.7 GND 0.1 0.2 -300 -1.0 -1.5 -2 -2 Test conditions Min. Limits Typ. 5.0 3.0 5.5 VDD-2 VDD-0.1 VDD-0.2 500 1.0 1.5 2 2 0.1 V A LSB LSB LSB LSB F Max. Unit mA V V MITSUBISHI ELECTRIC ( 4/5) MITSUBISHI M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS AC CHARACTERISTICS(VCC=VDD,Ta=-20 ~ +85C,unless otherwise noted) Symbol tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDo tLDD Parameter Clock "L"pulse width Clock "H"pulse width Clock rise time Clock fall time Data set up time Data hold time LD set up time LD hold time LD "H" pulse duration Data output delay time D-A converter output setting time CL=100pF CL100pF,VAO:0.3 2.7V The time until the output becomes the final value of 2 LSB Test conditions Min 200 200 Limits Typ Max Unit ns ns ns ns ns ns ns ns ns 200 200 30 60 200 100 100 70 350 100 ns s TIMING CHART tCR tCKH tCF CLK tCKL DI tDCH tCHD tLDH tCHL LD tLDC tLDD D-A OUTPUT tDo Do OUTPUT MITSUBISHI ELECTRIC ( 5/5) |
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